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([2a01:e0a:982:cbb0:ba23:8574:fa8:28dd]) by smtp.gmail.com with ESMTPSA id g14-20020a05600c4ece00b0040fe4b733f4sm930244wmq.26.2024.02.06.01.00.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 Feb 2024 01:00:06 -0800 (PST) Message-ID: Date: Tue, 6 Feb 2024 10:00:05 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCHv1 4/5] arm64: dts: amlogic: Add cache information to the Amlogic S922X SoC Content-Language: en-US, fr To: Anand Moon , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kevin Hilman , Jerome Brunet , Martin Blumenstingl Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org References: <20240205171930.968-1-linux.amoon@gmail.com> <20240205171930.968-5-linux.amoon@gmail.com> Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro Developer Services In-Reply-To: <20240205171930.968-5-linux.amoon@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 05/02/2024 18:19, Anand Moon wrote: > As per S922X datasheet add missing cache information to the Amlogic > S922X SoC. > > - Each Cortex-A53 core has 32 KB of instruction cache and > 32 KB of L1 data cache available. > - Each Cortex-A73 core has 64 KB of L1 instruction cache and > 64 KB of L1 data cache available. > - The little (A53) cluster has 512 KB of unified L2 cache available. > - The big (A73) cluster has 1 MB of unified L2 cache available. Datasheet says: The quad core Cortex™-A73 processor is paired with A53 processor in a big.Little configuration, with each core has L1 instruction and data chaches, together with a single shared L2 unified cache with A53 And there's no indication of the L1 or L2 cache sizes. Neil > > To improve system performance. > > Signed-off-by: Anand Moon > --- > [0] https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf > [1] https://en.wikipedia.org/wiki/ARM_Cortex-A73 > [2] https://en.wikipedia.org/wiki/ARM_Cortex-A53 > --- > arch/arm64/boot/dts/amlogic/meson-g12b.dtsi | 62 ++++++++++++++++++--- > 1 file changed, 55 insertions(+), 7 deletions(-) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi > index 86e6ceb31d5e..624c6fd763ac 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-g12b.dtsi > @@ -49,7 +49,13 @@ cpu0: cpu@0 { > reg = <0x0 0x0>; > enable-method = "psci"; > capacity-dmips-mhz = <592>; > - next-level-cache = <&l2>; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l2_cache_l>; > #cooling-cells = <2>; > }; > > @@ -59,7 +65,13 @@ cpu1: cpu@1 { > reg = <0x0 0x1>; > enable-method = "psci"; > capacity-dmips-mhz = <592>; > - next-level-cache = <&l2>; > + d-cache-line-size = <32>; > + d-cache-size = <0x8000>; > + d-cache-sets = <32>; > + i-cache-line-size = <32>; > + i-cache-size = <0x8000>; > + i-cache-sets = <32>; > + next-level-cache = <&l2_cache_l>; > #cooling-cells = <2>; > }; > > @@ -69,7 +81,13 @@ cpu100: cpu@100 { > reg = <0x0 0x100>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > - next-level-cache = <&l2>; > + d-cache-line-size = <64>; > + d-cache-size = <0x10000>; > + d-cache-sets = <64>; > + i-cache-line-size = <64>; > + i-cache-size = <0x10000>; > + i-cache-sets = <64>; > + next-level-cache = <&l2_cache_b>; > #cooling-cells = <2>; > }; > > @@ -79,7 +97,13 @@ cpu101: cpu@101 { > reg = <0x0 0x101>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > - next-level-cache = <&l2>; > + d-cache-line-size = <64>; > + d-cache-size = <0x10000>; > + d-cache-sets = <64>; > + i-cache-line-size = <64>; > + i-cache-size = <0x10000>; > + i-cache-sets = <64>; > + next-level-cache = <&l2_cache_b>; > #cooling-cells = <2>; > }; > > @@ -89,7 +113,13 @@ cpu102: cpu@102 { > reg = <0x0 0x102>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > - next-level-cache = <&l2>; > + d-cache-line-size = <64>; > + d-cache-size = <0x10000>; > + d-cache-sets = <64>; > + i-cache-line-size = <64>; > + i-cache-size = <0x10000>; > + i-cache-sets = <64>; > + next-level-cache = <&l2_cache_b>; > #cooling-cells = <2>; > }; > > @@ -99,14 +129,32 @@ cpu103: cpu@103 { > reg = <0x0 0x103>; > enable-method = "psci"; > capacity-dmips-mhz = <1024>; > - next-level-cache = <&l2>; > + d-cache-line-size = <64>; > + d-cache-size = <0x10000>; > + d-cache-sets = <64>; > + i-cache-line-size = <64>; > + i-cache-size = <0x10000>; > + i-cache-sets = <64>; > + next-level-cache = <&l2_cache_b>; > #cooling-cells = <2>; > }; > > - l2: l2-cache0 { > + l2_cache_l: l2-cache-cluster0 { > compatible = "cache"; > cache-level = <2>; > cache-unified; > + cache-size = <0x80000>; > + cache-line-size = <64>; > + cache-sets = <512>; > + }; > + > + l2_cache_b: l2-cache-cluster1 { > + compatible = "cache"; > + cache-level = <2>; > + cache-unified; > + cache-size = <0x100000>; > + cache-line-size = <64>; > + cache-sets = <512>; > }; > }; > };