* [PATCH v2 0/5] arm64: dts: exynos2200: introduce serial busses, except spi
@ 2025-07-30 7:42 Ivaylo Ivanov
2025-07-30 7:42 ` [PATCH v2 1/5] arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label Ivaylo Ivanov
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Ivaylo Ivanov @ 2025-07-30 7:42 UTC (permalink / raw)
To: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley
Cc: linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel
Hey, folks!
Before anything, this patchset only has binding dependencies, without
which it will have undocumented compatibles. They are the following:
[1] - https://lore.kernel.org/all/20250730072730.1882549-1-ivo.ivanov.ivanov1@gmail.com/
This patchset adds serial busses, implemented in usi, as well as serial_0
and serial_1 for exynos2200. It's missing spi, due to me having troubles
with reads when testing.
Best regards,
Ivaylo
Changes in v2:
- add a patch that switches address and size cells to 1 in /soc
- adjust all new nodes to define reg props with 2 cells in total instead of 4
Ivaylo Ivanov (5):
arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label
arm64: dts: exynos2200: use 32-bit address space for /soc
arm64: dts: exynos2200: increase peric1 and cmgp syscon sizes
arm64: dts: exynos2200: add serial_0/1 nodes
arm64: dts: exynos2200: define all usi nodes
.../boot/dts/exynos/exynos2200-pinctrl.dtsi | 2 +-
arch/arm64/boot/dts/exynos/exynos2200.dtsi | 1459 ++++++++++++++++-
2 files changed, 1424 insertions(+), 37 deletions(-)
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH v2 1/5] arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label 2025-07-30 7:42 [PATCH v2 0/5] arm64: dts: exynos2200: introduce serial busses, except spi Ivaylo Ivanov @ 2025-07-30 7:42 ` Ivaylo Ivanov 2025-08-01 20:59 ` Sam Protsenko 2025-07-30 7:42 ` [PATCH v2 2/5] arm64: dts: exynos2200: use 32-bit address space for /soc Ivaylo Ivanov ` (3 subsequent siblings) 4 siblings, 1 reply; 14+ messages in thread From: Ivaylo Ivanov @ 2025-07-30 7:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley Cc: linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel The '2' in 'hsi2c23' was missed while making the device tree. Fix that so we can properly reference the node. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> --- arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi index f618ff290..5877da7ba 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi @@ -1438,7 +1438,7 @@ i3c11_bus: i3c11-bus-pins { samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; }; - hsi223_bus: hsi2c23-bus-pins { + hsi2c23_bus: hsi2c23-bus-pins { samsung,pins = "gpp11-2", "gpp11-3"; samsung,pin-function = <EXYNOS_PIN_FUNC_3>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; -- 2.43.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 1/5] arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label 2025-07-30 7:42 ` [PATCH v2 1/5] arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label Ivaylo Ivanov @ 2025-08-01 20:59 ` Sam Protsenko 0 siblings, 0 replies; 14+ messages in thread From: Sam Protsenko @ 2025-08-01 20:59 UTC (permalink / raw) To: Ivaylo Ivanov Cc: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley, linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel On Wed, Jul 30, 2025 at 2:43 AM Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> wrote: > > The '2' in 'hsi2c23' was missed while making the device tree. Fix that so > we can properly reference the node. > > Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > --- Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi > index f618ff290..5877da7ba 100644 > --- a/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos2200-pinctrl.dtsi > @@ -1438,7 +1438,7 @@ i3c11_bus: i3c11-bus-pins { > samsung,pin-drv = <EXYNOS7_PIN_DRV_LV1>; > }; > > - hsi223_bus: hsi2c23-bus-pins { > + hsi2c23_bus: hsi2c23-bus-pins { > samsung,pins = "gpp11-2", "gpp11-3"; > samsung,pin-function = <EXYNOS_PIN_FUNC_3>; > samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; > -- > 2.43.0 > > ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 2/5] arm64: dts: exynos2200: use 32-bit address space for /soc 2025-07-30 7:42 [PATCH v2 0/5] arm64: dts: exynos2200: introduce serial busses, except spi Ivaylo Ivanov 2025-07-30 7:42 ` [PATCH v2 1/5] arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label Ivaylo Ivanov @ 2025-07-30 7:42 ` Ivaylo Ivanov 2025-08-01 21:16 ` Sam Protsenko 2025-07-30 7:42 ` [PATCH v2 3/5] arm64: dts: exynos2200: increase peric1 and cmgp syscon sizes Ivaylo Ivanov ` (2 subsequent siblings) 4 siblings, 1 reply; 14+ messages in thread From: Ivaylo Ivanov @ 2025-07-30 7:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley Cc: linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel All peripherals on this SoC are mapped under the 32-bit address space (0x0 -> 0x20000000), so enforce that. Suggested-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> --- This was suggested at [1]. [1] https://lore.kernel.org/all/CAPLW+4kPN65uX0tyG_F-4u5FQpPnwX9y6F1zrobq5UyVbks+-w@mail.gmail.com --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 72 +++++++++++----------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi index 6b5ac02d0..943e83851 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -221,22 +221,22 @@ psci { method = "smc"; }; - soc { + soc@0 { compatible = "simple-bus"; - ranges; + ranges = <0x0 0x0 0x0 0x20000000>; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; chipid@10000000 { compatible = "samsung,exynos2200-chipid", "samsung,exynos850-chipid"; - reg = <0x0 0x10000000 0x0 0x24>; + reg = <0x10000000 0x24>; }; cmu_peris: clock-controller@10020000 { compatible = "samsung,exynos2200-cmu-peris"; - reg = <0x0 0x10020000 0x0 0x8000>; + reg = <0x10020000 0x8000>; #clock-cells = <1>; clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, @@ -250,7 +250,7 @@ cmu_peris: clock-controller@10020000 { mct_peris: timer@10040000 { compatible = "samsung,exynos2200-mct-peris", "samsung,exynos4210-mct"; - reg = <0x0 0x10040000 0x0 0x800>; + reg = <0x10040000 0x800>; clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, <&cmu_peris CLK_MOUT_PERIS_GIC>; clock-names = "fin_pll", "mct"; interrupts = <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH 0>, @@ -270,8 +270,8 @@ mct_peris: timer@10040000 { gic: interrupt-controller@10200000 { compatible = "arm,gic-v3"; - reg = <0x0 0x10200000 0x0 0x10000>, /* GICD */ - <0x0 0x10240000 0x0 0x200000>; /* GICR * 8 */ + reg = <0x10200000 0x10000>, /* GICD */ + <0x10240000 0x200000>; /* GICR * 8 */ #interrupt-cells = <4>; interrupt-controller; @@ -294,7 +294,7 @@ ppi_cluster2: interrupt-partition-2 { cmu_peric0: clock-controller@10400000 { compatible = "samsung,exynos2200-cmu-peric0"; - reg = <0x0 0x10400000 0x0 0x8000>; + reg = <0x10400000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -306,17 +306,17 @@ cmu_peric0: clock-controller@10400000 { syscon_peric0: syscon@10420000 { compatible = "samsung,exynos2200-peric0-sysreg", "syscon"; - reg = <0x0 0x10420000 0x0 0x2000>; + reg = <0x10420000 0x2000>; }; pinctrl_peric0: pinctrl@10430000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x10430000 0x0 0x1000>; + reg = <0x10430000 0x1000>; }; cmu_peric1: clock-controller@10700000 { compatible = "samsung,exynos2200-cmu-peric1"; - reg = <0x0 0x10700000 0x0 0x8000>; + reg = <0x10700000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -328,23 +328,23 @@ cmu_peric1: clock-controller@10700000 { syscon_peric1: syscon@10720000 { compatible = "samsung,exynos2200-peric1-sysreg", "syscon"; - reg = <0x0 0x10720000 0x0 0x2000>; + reg = <0x10720000 0x2000>; }; pinctrl_peric1: pinctrl@10730000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x10730000 0x0 0x1000>; + reg = <0x10730000 0x1000>; }; cmu_hsi0: clock-controller@10a00000 { compatible = "samsung,exynos2200-cmu-hsi0"; - reg = <0x0 0x10a00000 0x0 0x8000>; + reg = <0x10a00000 0x8000>; #clock-cells = <1>; }; usb32drd: phy@10aa0000 { compatible = "samsung,exynos2200-usb32drd-phy"; - reg = <0x0 0x10aa0000 0x0 0x10000>; + reg = <0x10aa0000 0x10000>; clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; clock-names = "phy"; @@ -360,7 +360,7 @@ usb32drd: phy@10aa0000 { usb_hsphy: phy@10ab0000 { compatible = "samsung,exynos2200-eusb2-phy"; - reg = <0x0 0x10ab0000 0x0 0x10000>; + reg = <0x10ab0000 0x10000>; clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>, <&cmu_hsi0 CLK_MOUT_HSI0_NOC>, @@ -374,7 +374,7 @@ usb_hsphy: phy@10ab0000 { usb: usb@10b00000 { compatible = "samsung,exynos2200-dwusb3"; - ranges = <0x0 0x0 0x10b00000 0x10000>; + ranges = <0x0 0x10b00000 0x10000>; clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; clock-names = "link_aclk"; @@ -406,7 +406,7 @@ usb_dwc3: usb@0 { cmu_ufs: clock-controller@11000000 { compatible = "samsung,exynos2200-cmu-ufs"; - reg = <0x0 0x11000000 0x0 0x8000>; + reg = <0x11000000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -418,27 +418,27 @@ cmu_ufs: clock-controller@11000000 { syscon_ufs: syscon@11020000 { compatible = "samsung,exynos2200-ufs-sysreg", "syscon"; - reg = <0x0 0x11020000 0x0 0x2000>; + reg = <0x11020000 0x2000>; }; pinctrl_ufs: pinctrl@11040000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x11040000 0x0 0x1000>; + reg = <0x11040000 0x1000>; }; pinctrl_hsi1ufs: pinctrl@11060000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x11060000 0x0 0x1000>; + reg = <0x11060000 0x1000>; }; pinctrl_hsi1: pinctrl@11240000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x11240000 0x0 0x1000>; + reg = <0x11240000 0x1000>; }; cmu_peric2: clock-controller@11c00000 { compatible = "samsung,exynos2200-cmu-peric2"; - reg = <0x0 0x11c00000 0x0 0x8000>; + reg = <0x11c00000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -450,17 +450,17 @@ cmu_peric2: clock-controller@11c00000 { syscon_peric2: syscon@11c20000 { compatible = "samsung,exynos2200-peric2-sysreg", "syscon"; - reg = <0x0 0x11c20000 0x0 0x4000>; + reg = <0x11c20000 0x4000>; }; pinctrl_peric2: pinctrl@11c30000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x11c30000 0x0 0x1000>; + reg = <0x11c30000 0x1000>; }; cmu_cmgp: clock-controller@14e00000 { compatible = "samsung,exynos2200-cmu-cmgp"; - reg = <0x0 0x14e00000 0x0 0x8000>; + reg = <0x14e00000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -471,12 +471,12 @@ cmu_cmgp: clock-controller@14e00000 { syscon_cmgp: syscon@14e20000 { compatible = "samsung,exynos2200-cmgp-sysreg", "syscon"; - reg = <0x0 0x14e20000 0x0 0x2000>; + reg = <0x14e20000 0x2000>; }; pinctrl_cmgp: pinctrl@14e30000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x14e30000 0x0 0x1000>; + reg = <0x14e30000 0x1000>; wakeup-interrupt-controller { compatible = "samsung,exynos2200-wakeup-eint", @@ -487,7 +487,7 @@ wakeup-interrupt-controller { cmu_vts: clock-controller@15300000 { compatible = "samsung,exynos2200-cmu-vts"; - reg = <0x0 0x15300000 0x0 0x8000>; + reg = <0x15300000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -497,12 +497,12 @@ cmu_vts: clock-controller@15300000 { pinctrl_vts: pinctrl@15320000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x15320000 0x0 0x1000>; + reg = <0x15320000 0x1000>; }; cmu_alive: clock-controller@15800000 { compatible = "samsung,exynos2200-cmu-alive"; - reg = <0x0 0x15800000 0x0 0x8000>; + reg = <0x15800000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>, @@ -512,7 +512,7 @@ cmu_alive: clock-controller@15800000 { pinctrl_alive: pinctrl@15850000 { compatible = "samsung,exynos2200-pinctrl"; - reg = <0x0 0x15850000 0x0 0x1000>; + reg = <0x15850000 0x1000>; wakeup-interrupt-controller { compatible = "samsung,exynos2200-wakeup-eint", @@ -524,7 +524,7 @@ wakeup-interrupt-controller { pmu_system_controller: system-controller@15860000 { compatible = "samsung,exynos2200-pmu", "samsung,exynos7-pmu", "syscon"; - reg = <0x0 0x15860000 0x0 0x10000>; + reg = <0x15860000 0x10000>; reboot: syscon-reboot { compatible = "syscon-reboot"; @@ -536,7 +536,7 @@ reboot: syscon-reboot { cmu_top: clock-controller@1a320000 { compatible = "samsung,exynos2200-cmu-top"; - reg = <0x0 0x1a320000 0x0 0x8000>; + reg = <0x1a320000 0x8000>; #clock-cells = <1>; clocks = <&xtcxo>; -- 2.43.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 2/5] arm64: dts: exynos2200: use 32-bit address space for /soc 2025-07-30 7:42 ` [PATCH v2 2/5] arm64: dts: exynos2200: use 32-bit address space for /soc Ivaylo Ivanov @ 2025-08-01 21:16 ` Sam Protsenko 0 siblings, 0 replies; 14+ messages in thread From: Sam Protsenko @ 2025-08-01 21:16 UTC (permalink / raw) To: Ivaylo Ivanov Cc: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley, linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel On Wed, Jul 30, 2025 at 2:43 AM Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> wrote: > > All peripherals on this SoC are mapped under the 32-bit address space > (0x0 -> 0x20000000), so enforce that. > > Suggested-by: Sam Protsenko <semen.protsenko@linaro.org> > Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > > --- > This was suggested at [1]. > > [1] https://lore.kernel.org/all/CAPLW+4kPN65uX0tyG_F-4u5FQpPnwX9y6F1zrobq5UyVbks+-w@mail.gmail.com > --- Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > arch/arm64/boot/dts/exynos/exynos2200.dtsi | 72 +++++++++++----------- > 1 file changed, 36 insertions(+), 36 deletions(-) > > diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi > index 6b5ac02d0..943e83851 100644 > --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi > @@ -221,22 +221,22 @@ psci { > method = "smc"; > }; > > - soc { > + soc@0 { > compatible = "simple-bus"; > - ranges; > + ranges = <0x0 0x0 0x0 0x20000000>; > > - #address-cells = <2>; > - #size-cells = <2>; > + #address-cells = <1>; > + #size-cells = <1>; > > chipid@10000000 { > compatible = "samsung,exynos2200-chipid", > "samsung,exynos850-chipid"; > - reg = <0x0 0x10000000 0x0 0x24>; > + reg = <0x10000000 0x24>; > }; > > cmu_peris: clock-controller@10020000 { > compatible = "samsung,exynos2200-cmu-peris"; > - reg = <0x0 0x10020000 0x0 0x8000>; > + reg = <0x10020000 0x8000>; > #clock-cells = <1>; > > clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, > @@ -250,7 +250,7 @@ cmu_peris: clock-controller@10020000 { > mct_peris: timer@10040000 { > compatible = "samsung,exynos2200-mct-peris", > "samsung,exynos4210-mct"; > - reg = <0x0 0x10040000 0x0 0x800>; > + reg = <0x10040000 0x800>; > clocks = <&cmu_top CLK_DOUT_TCXO_DIV3>, <&cmu_peris CLK_MOUT_PERIS_GIC>; > clock-names = "fin_pll", "mct"; > interrupts = <GIC_SPI 943 IRQ_TYPE_LEVEL_HIGH 0>, > @@ -270,8 +270,8 @@ mct_peris: timer@10040000 { > > gic: interrupt-controller@10200000 { > compatible = "arm,gic-v3"; > - reg = <0x0 0x10200000 0x0 0x10000>, /* GICD */ > - <0x0 0x10240000 0x0 0x200000>; /* GICR * 8 */ > + reg = <0x10200000 0x10000>, /* GICD */ > + <0x10240000 0x200000>; /* GICR * 8 */ > > #interrupt-cells = <4>; > interrupt-controller; > @@ -294,7 +294,7 @@ ppi_cluster2: interrupt-partition-2 { > > cmu_peric0: clock-controller@10400000 { > compatible = "samsung,exynos2200-cmu-peric0"; > - reg = <0x0 0x10400000 0x0 0x8000>; > + reg = <0x10400000 0x8000>; > #clock-cells = <1>; > > clocks = <&xtcxo>, > @@ -306,17 +306,17 @@ cmu_peric0: clock-controller@10400000 { > > syscon_peric0: syscon@10420000 { > compatible = "samsung,exynos2200-peric0-sysreg", "syscon"; > - reg = <0x0 0x10420000 0x0 0x2000>; > + reg = <0x10420000 0x2000>; > }; > > pinctrl_peric0: pinctrl@10430000 { > compatible = "samsung,exynos2200-pinctrl"; > - reg = <0x0 0x10430000 0x0 0x1000>; > + reg = <0x10430000 0x1000>; > }; > > cmu_peric1: clock-controller@10700000 { > compatible = "samsung,exynos2200-cmu-peric1"; > - reg = <0x0 0x10700000 0x0 0x8000>; > + reg = <0x10700000 0x8000>; > #clock-cells = <1>; > > clocks = <&xtcxo>, > @@ -328,23 +328,23 @@ cmu_peric1: clock-controller@10700000 { > > syscon_peric1: syscon@10720000 { > compatible = "samsung,exynos2200-peric1-sysreg", "syscon"; > - reg = <0x0 0x10720000 0x0 0x2000>; > + reg = <0x10720000 0x2000>; > }; > > pinctrl_peric1: pinctrl@10730000 { > compatible = "samsung,exynos2200-pinctrl"; > - reg = <0x0 0x10730000 0x0 0x1000>; > + reg = <0x10730000 0x1000>; > }; > > cmu_hsi0: clock-controller@10a00000 { > compatible = "samsung,exynos2200-cmu-hsi0"; > - reg = <0x0 0x10a00000 0x0 0x8000>; > + reg = <0x10a00000 0x8000>; > #clock-cells = <1>; > }; > > usb32drd: phy@10aa0000 { > compatible = "samsung,exynos2200-usb32drd-phy"; > - reg = <0x0 0x10aa0000 0x0 0x10000>; > + reg = <0x10aa0000 0x10000>; > > clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; > clock-names = "phy"; > @@ -360,7 +360,7 @@ usb32drd: phy@10aa0000 { > > usb_hsphy: phy@10ab0000 { > compatible = "samsung,exynos2200-eusb2-phy"; > - reg = <0x0 0x10ab0000 0x0 0x10000>; > + reg = <0x10ab0000 0x10000>; > > clocks = <&cmu_hsi0 CLK_MOUT_HSI0_USB32DRD>, > <&cmu_hsi0 CLK_MOUT_HSI0_NOC>, > @@ -374,7 +374,7 @@ usb_hsphy: phy@10ab0000 { > > usb: usb@10b00000 { > compatible = "samsung,exynos2200-dwusb3"; > - ranges = <0x0 0x0 0x10b00000 0x10000>; > + ranges = <0x0 0x10b00000 0x10000>; > > clocks = <&cmu_hsi0 CLK_MOUT_HSI0_NOC>; > clock-names = "link_aclk"; > @@ -406,7 +406,7 @@ usb_dwc3: usb@0 { > > cmu_ufs: clock-controller@11000000 { > compatible = "samsung,exynos2200-cmu-ufs"; > - reg = <0x0 0x11000000 0x0 0x8000>; > + reg = <0x11000000 0x8000>; > #clock-cells = <1>; > > clocks = <&xtcxo>, > @@ -418,27 +418,27 @@ cmu_ufs: clock-controller@11000000 { > > syscon_ufs: syscon@11020000 { > compatible = "samsung,exynos2200-ufs-sysreg", "syscon"; > - reg = <0x0 0x11020000 0x0 0x2000>; > + reg = <0x11020000 0x2000>; > }; > > pinctrl_ufs: pinctrl@11040000 { > compatible = "samsung,exynos2200-pinctrl"; > - reg = <0x0 0x11040000 0x0 0x1000>; > + reg = <0x11040000 0x1000>; > }; > > pinctrl_hsi1ufs: pinctrl@11060000 { > compatible = "samsung,exynos2200-pinctrl"; > - reg = <0x0 0x11060000 0x0 0x1000>; > + reg = <0x11060000 0x1000>; > }; > > pinctrl_hsi1: pinctrl@11240000 { > compatible = "samsung,exynos2200-pinctrl"; > - reg = <0x0 0x11240000 0x0 0x1000>; > + reg = <0x11240000 0x1000>; > }; > > cmu_peric2: clock-controller@11c00000 { > compatible = "samsung,exynos2200-cmu-peric2"; > - reg = <0x0 0x11c00000 0x0 0x8000>; > + reg = <0x11c00000 0x8000>; > #clock-cells = <1>; > > clocks = <&xtcxo>, > @@ -450,17 +450,17 @@ cmu_peric2: clock-controller@11c00000 { > > syscon_peric2: syscon@11c20000 { > compatible = "samsung,exynos2200-peric2-sysreg", "syscon"; > - reg = <0x0 0x11c20000 0x0 0x4000>; > + reg = <0x11c20000 0x4000>; > }; > > pinctrl_peric2: pinctrl@11c30000 { > compatible = "samsung,exynos2200-pinctrl"; > - reg = <0x0 0x11c30000 0x0 0x1000>; > + reg = <0x11c30000 0x1000>; > }; > > cmu_cmgp: clock-controller@14e00000 { > compatible = "samsung,exynos2200-cmu-cmgp"; > - reg = <0x0 0x14e00000 0x0 0x8000>; > + reg = <0x14e00000 0x8000>; > #clock-cells = <1>; > > clocks = <&xtcxo>, > @@ -471,12 +471,12 @@ cmu_cmgp: clock-controller@14e00000 { > > syscon_cmgp: syscon@14e20000 { > compatible = "samsung,exynos2200-cmgp-sysreg", "syscon"; > - reg = <0x0 0x14e20000 0x0 0x2000>; > + reg = <0x14e20000 0x2000>; > }; > > pinctrl_cmgp: pinctrl@14e30000 { > compatible = "samsung,exynos2200-pinctrl"; > - reg = <0x0 0x14e30000 0x0 0x1000>; > + reg = <0x14e30000 0x1000>; > > wakeup-interrupt-controller { > compatible = "samsung,exynos2200-wakeup-eint", > @@ -487,7 +487,7 @@ wakeup-interrupt-controller { > > cmu_vts: clock-controller@15300000 { > compatible = "samsung,exynos2200-cmu-vts"; > - reg = <0x0 0x15300000 0x0 0x8000>; > + reg = <0x15300000 0x8000>; > #clock-cells = <1>; > > clocks = <&xtcxo>, > @@ -497,12 +497,12 @@ cmu_vts: clock-controller@15300000 { > > pinctrl_vts: pinctrl@15320000 { > compatible = "samsung,exynos2200-pinctrl"; > - reg = <0x0 0x15320000 0x0 0x1000>; > + reg = <0x15320000 0x1000>; > }; > > cmu_alive: clock-controller@15800000 { > compatible = "samsung,exynos2200-cmu-alive"; > - reg = <0x0 0x15800000 0x0 0x8000>; > + reg = <0x15800000 0x8000>; > #clock-cells = <1>; > > clocks = <&xtcxo>, > @@ -512,7 +512,7 @@ cmu_alive: clock-controller@15800000 { > > pinctrl_alive: pinctrl@15850000 { > compatible = "samsung,exynos2200-pinctrl"; > - reg = <0x0 0x15850000 0x0 0x1000>; > + reg = <0x15850000 0x1000>; > > wakeup-interrupt-controller { > compatible = "samsung,exynos2200-wakeup-eint", > @@ -524,7 +524,7 @@ wakeup-interrupt-controller { > pmu_system_controller: system-controller@15860000 { > compatible = "samsung,exynos2200-pmu", > "samsung,exynos7-pmu", "syscon"; > - reg = <0x0 0x15860000 0x0 0x10000>; > + reg = <0x15860000 0x10000>; > > reboot: syscon-reboot { > compatible = "syscon-reboot"; > @@ -536,7 +536,7 @@ reboot: syscon-reboot { > > cmu_top: clock-controller@1a320000 { > compatible = "samsung,exynos2200-cmu-top"; > - reg = <0x0 0x1a320000 0x0 0x8000>; > + reg = <0x1a320000 0x8000>; > #clock-cells = <1>; > > clocks = <&xtcxo>; > -- > 2.43.0 > > ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 3/5] arm64: dts: exynos2200: increase peric1 and cmgp syscon sizes 2025-07-30 7:42 [PATCH v2 0/5] arm64: dts: exynos2200: introduce serial busses, except spi Ivaylo Ivanov 2025-07-30 7:42 ` [PATCH v2 1/5] arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label Ivaylo Ivanov 2025-07-30 7:42 ` [PATCH v2 2/5] arm64: dts: exynos2200: use 32-bit address space for /soc Ivaylo Ivanov @ 2025-07-30 7:42 ` Ivaylo Ivanov 2025-08-01 22:11 ` Sam Protsenko 2025-07-30 7:42 ` [PATCH v2 4/5] arm64: dts: exynos2200: add serial_0/1 nodes Ivaylo Ivanov 2025-07-30 7:42 ` [PATCH v2 5/5] arm64: dts: exynos2200: define all usi nodes Ivaylo Ivanov 4 siblings, 1 reply; 14+ messages in thread From: Ivaylo Ivanov @ 2025-07-30 7:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley Cc: linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel Some USI instances have swconfig offsets that reside over the currently defined syscon ranges for peric1 and cmgp. Increase their sizes. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi index 943e83851..bab77b442 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -328,7 +328,7 @@ cmu_peric1: clock-controller@10700000 { syscon_peric1: syscon@10720000 { compatible = "samsung,exynos2200-peric1-sysreg", "syscon"; - reg = <0x10720000 0x2000>; + reg = <0x10720000 0x3000>; }; pinctrl_peric1: pinctrl@10730000 { @@ -471,7 +471,7 @@ cmu_cmgp: clock-controller@14e00000 { syscon_cmgp: syscon@14e20000 { compatible = "samsung,exynos2200-cmgp-sysreg", "syscon"; - reg = <0x14e20000 0x2000>; + reg = <0x14e20000 0x3000>; }; pinctrl_cmgp: pinctrl@14e30000 { -- 2.43.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 3/5] arm64: dts: exynos2200: increase peric1 and cmgp syscon sizes 2025-07-30 7:42 ` [PATCH v2 3/5] arm64: dts: exynos2200: increase peric1 and cmgp syscon sizes Ivaylo Ivanov @ 2025-08-01 22:11 ` Sam Protsenko 2025-08-06 14:05 ` Ivaylo Ivanov 0 siblings, 1 reply; 14+ messages in thread From: Sam Protsenko @ 2025-08-01 22:11 UTC (permalink / raw) To: Ivaylo Ivanov Cc: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley, linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel On Wed, Jul 30, 2025 at 2:43 AM Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> wrote: > > Some USI instances have swconfig offsets that reside over the currently > defined syscon ranges for peric1 and cmgp. Increase their sizes. > > Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > --- Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > arch/arm64/boot/dts/exynos/exynos2200.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi > index 943e83851..bab77b442 100644 > --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi > @@ -328,7 +328,7 @@ cmu_peric1: clock-controller@10700000 { > > syscon_peric1: syscon@10720000 { > compatible = "samsung,exynos2200-peric1-sysreg", "syscon"; > - reg = <0x10720000 0x2000>; > + reg = <0x10720000 0x3000>; Exynos850 TRM says that all System Register instances (in Exynos850 SoC) use 16 KiB (0x4000) of address space for their registers. And I can see some SYSREG registers actually have offsets over 0x3000. In reality though all IP cores are aligned by 0x10000. I have a feeling Samsung does the IP cores integration in the same way for all their modern Exynos SoCs. It can be actually deduced by looking at the starting addresses of the nodes in the device tree, they are always aligned by 0x10000. Hence I'd recommend doing this: 1. Use either 0x4000 or 0x10000 size (not 0x3000). For the reference, Exynos850 and gs101 use 0x10000 value. 2. Replace the size values for all sysreg nodes in your device tree (not only peric1 and cmgp), for consistency and to prevent possible issues in future. Also, maybe it'd be better to use "sysreg_" prefix for these node labels (not "syscon_"), as it's called System Register in TRM. But that's minor, and probably out of scope for this patch. > }; > > pinctrl_peric1: pinctrl@10730000 { > @@ -471,7 +471,7 @@ cmu_cmgp: clock-controller@14e00000 { > > syscon_cmgp: syscon@14e20000 { > compatible = "samsung,exynos2200-cmgp-sysreg", "syscon"; > - reg = <0x14e20000 0x2000>; > + reg = <0x14e20000 0x3000>; > }; > > pinctrl_cmgp: pinctrl@14e30000 { > -- > 2.43.0 > > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 3/5] arm64: dts: exynos2200: increase peric1 and cmgp syscon sizes 2025-08-01 22:11 ` Sam Protsenko @ 2025-08-06 14:05 ` Ivaylo Ivanov 0 siblings, 0 replies; 14+ messages in thread From: Ivaylo Ivanov @ 2025-08-06 14:05 UTC (permalink / raw) To: Sam Protsenko Cc: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley, linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel On 8/2/25 01:11, Sam Protsenko wrote: > On Wed, Jul 30, 2025 at 2:43 AM Ivaylo Ivanov > <ivo.ivanov.ivanov1@gmail.com> wrote: >> Some USI instances have swconfig offsets that reside over the currently >> defined syscon ranges for peric1 and cmgp. Increase their sizes. >> >> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >> --- > Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> > >> arch/arm64/boot/dts/exynos/exynos2200.dtsi | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi >> index 943e83851..bab77b442 100644 >> --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi >> +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi >> @@ -328,7 +328,7 @@ cmu_peric1: clock-controller@10700000 { >> >> syscon_peric1: syscon@10720000 { >> compatible = "samsung,exynos2200-peric1-sysreg", "syscon"; >> - reg = <0x10720000 0x2000>; >> + reg = <0x10720000 0x3000>; > Exynos850 TRM says that all System Register instances (in Exynos850 > SoC) use 16 KiB (0x4000) of address space for their registers. And I > can see some SYSREG registers actually have offsets over 0x3000. In > reality though all IP cores are aligned by 0x10000. I have a feeling > Samsung does the IP cores integration in the same way for all their > modern Exynos SoCs. It can be actually deduced by looking at the > starting addresses of the nodes in the device tree, they are always > aligned by 0x10000. > > Hence I'd recommend doing this: > 1. Use either 0x4000 or 0x10000 size (not 0x3000). For the > reference, Exynos850 and gs101 use 0x10000 value. > 2. Replace the size values for all sysreg nodes in your device tree > (not only peric1 and cmgp), for consistency and to prevent possible > issues in future. Alright, thanks. > > Also, maybe it'd be better to use "sysreg_" prefix for these node > labels (not "syscon_"), as it's called System Register in TRM. But > that's minor, and probably out of scope for this patch. Does not matter that much imo, just a label. You could make a patch to rename it on other trees too. Best regards, Ivaylo > >> }; >> >> pinctrl_peric1: pinctrl@10730000 { >> @@ -471,7 +471,7 @@ cmu_cmgp: clock-controller@14e00000 { >> >> syscon_cmgp: syscon@14e20000 { >> compatible = "samsung,exynos2200-cmgp-sysreg", "syscon"; >> - reg = <0x14e20000 0x2000>; >> + reg = <0x14e20000 0x3000>; >> }; >> >> pinctrl_cmgp: pinctrl@14e30000 { >> -- >> 2.43.0 >> >> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 4/5] arm64: dts: exynos2200: add serial_0/1 nodes 2025-07-30 7:42 [PATCH v2 0/5] arm64: dts: exynos2200: introduce serial busses, except spi Ivaylo Ivanov ` (2 preceding siblings ...) 2025-07-30 7:42 ` [PATCH v2 3/5] arm64: dts: exynos2200: increase peric1 and cmgp syscon sizes Ivaylo Ivanov @ 2025-07-30 7:42 ` Ivaylo Ivanov 2025-08-01 23:12 ` Sam Protsenko 2025-07-30 7:42 ` [PATCH v2 5/5] arm64: dts: exynos2200: define all usi nodes Ivaylo Ivanov 4 siblings, 1 reply; 14+ messages in thread From: Ivaylo Ivanov @ 2025-07-30 7:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley Cc: linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel Add nodes for serial_0 (UART_DBG) and serial_1 (UART_BT), which allows using them. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi index bab77b442..22c6da907 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -336,6 +336,19 @@ pinctrl_peric1: pinctrl@10730000 { reg = <0x10730000 0x1000>; }; + serial_1: serial@10840000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10840000 0x100>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_UART_BT>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart1_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + cmu_hsi0: clock-controller@10a00000 { compatible = "samsung,exynos2200-cmu-hsi0"; reg = <0x10a00000 0x8000>; @@ -458,6 +471,19 @@ pinctrl_peric2: pinctrl@11c30000 { reg = <0x11c30000 0x1000>; }; + serial_0: serial@11c40000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11c40000 0x100>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_UART_DBG>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart0_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + cmu_cmgp: clock-controller@14e00000 { compatible = "samsung,exynos2200-cmu-cmgp"; reg = <0x14e00000 0x8000>; -- 2.43.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: exynos2200: add serial_0/1 nodes 2025-07-30 7:42 ` [PATCH v2 4/5] arm64: dts: exynos2200: add serial_0/1 nodes Ivaylo Ivanov @ 2025-08-01 23:12 ` Sam Protsenko 2025-08-06 14:03 ` Ivaylo Ivanov 0 siblings, 1 reply; 14+ messages in thread From: Sam Protsenko @ 2025-08-01 23:12 UTC (permalink / raw) To: Ivaylo Ivanov Cc: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley, linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel On Wed, Jul 30, 2025 at 2:43 AM Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> wrote: > > Add nodes for serial_0 (UART_DBG) and serial_1 (UART_BT), which > allows using them. > > Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > --- > arch/arm64/boot/dts/exynos/exynos2200.dtsi | 26 ++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi > index bab77b442..22c6da907 100644 > --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi > @@ -336,6 +336,19 @@ pinctrl_peric1: pinctrl@10730000 { > reg = <0x10730000 0x1000>; > }; > > + serial_1: serial@10840000 { > + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; > + reg = <0x10840000 0x100>; > + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, > + <&cmu_peric1 CLK_DOUT_PERIC1_UART_BT>; > + clock-names = "uart", "clk_uart_baud0"; > + interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH 0>; > + pinctrl-0 = <&uart1_bus>; > + pinctrl-names = "default"; > + samsung,uart-fifosize = <256>; > + status = "disabled"; > + }; > + > cmu_hsi0: clock-controller@10a00000 { > compatible = "samsung,exynos2200-cmu-hsi0"; > reg = <0x10a00000 0x8000>; > @@ -458,6 +471,19 @@ pinctrl_peric2: pinctrl@11c30000 { > reg = <0x11c30000 0x1000>; > }; > > + serial_0: serial@11c40000 { > + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; > + reg = <0x11c40000 0x100>; > + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, > + <&cmu_peric2 CLK_DOUT_PERIC2_UART_DBG>; > + clock-names = "uart", "clk_uart_baud0"; > + interrupts = <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>; > + pinctrl-0 = <&uart0_bus_single>; > + pinctrl-names = "default"; > + samsung,uart-fifosize = <256>; > + status = "disabled"; > + }; > + Shouldn't these two serial nodes be children of some corresponding USI nodes? IIUC, the downstream counterpart of this device tree is [1]? I can see the corresponding USI node is missing there. And if you don't have the TRM, it might get confusing. But, apart from my intuition telling me that those UART blocks *should* be implemented as a part of USI IP blocks in Exynos2200, there is also a fact that the downstream driver is actually accessing USI registers in exynos_usi_init() function, in the exynos-uart driver here: [2]. If that's correct, it means there should exist a USI block, which should be modeled like so: 8<------------------------------------------------------------------------->8 usi_...: usi@11c400c0 { compatible = ...; reg = <0x138200c0 0x20>; samsung,sysreg = <...>; samsung,mode = <USI_MODE_UART>; #address-cells = <1>; #size-cells = <1>; ranges; clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, <&cmu_peric2 CLK_DOUT_PERIC2_UART_DBG>; clock-names = "pclk", "ipclk"; status = "disabled"; serial_0: serial@11c40000 { compatible = "samsung,exynos2200-uart", "google,gs101-uart"; reg = <0x11c40000 0x100>; clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, <&cmu_peric2 CLK_DOUT_PERIC2_UART_DBG>; clock-names = "uart", "clk_uart_baud0"; interrupts = <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-0 = <&uart0_bus_single>; pinctrl-names = "default"; samsung,uart-fifosize = <256>; status = "disabled"; }; }; 8<------------------------------------------------------------------------->8 This way you can achieve the same behavior as in downstream kernel, by making the (upstream) USI driver to initialize corresponding USI registers for you. Does that make any sense? Thanks! [1] https://github.com/jgudec/android_kernel_samsung_exynos2200/blob/CWAI/arch/arm64/boot/dts/exynos/s5e9925.dts#L4648 [2] https://github.com/jgudec/android_kernel_samsung_exynos2200/blob/CWAI/drivers/tty/serial/exynos_tty.c#L2181 > cmu_cmgp: clock-controller@14e00000 { > compatible = "samsung,exynos2200-cmu-cmgp"; > reg = <0x14e00000 0x8000>; > -- > 2.43.0 > > ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 4/5] arm64: dts: exynos2200: add serial_0/1 nodes 2025-08-01 23:12 ` Sam Protsenko @ 2025-08-06 14:03 ` Ivaylo Ivanov 0 siblings, 0 replies; 14+ messages in thread From: Ivaylo Ivanov @ 2025-08-06 14:03 UTC (permalink / raw) To: Sam Protsenko Cc: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley, linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel On 8/2/25 02:12, Sam Protsenko wrote: > On Wed, Jul 30, 2025 at 2:43 AM Ivaylo Ivanov > <ivo.ivanov.ivanov1@gmail.com> wrote: >> Add nodes for serial_0 (UART_DBG) and serial_1 (UART_BT), which >> allows using them. >> >> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >> --- >> arch/arm64/boot/dts/exynos/exynos2200.dtsi | 26 ++++++++++++++++++++++ >> 1 file changed, 26 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi >> index bab77b442..22c6da907 100644 >> --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi >> +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi >> @@ -336,6 +336,19 @@ pinctrl_peric1: pinctrl@10730000 { >> reg = <0x10730000 0x1000>; >> }; >> >> + serial_1: serial@10840000 { >> + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; >> + reg = <0x10840000 0x100>; >> + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, >> + <&cmu_peric1 CLK_DOUT_PERIC1_UART_BT>; >> + clock-names = "uart", "clk_uart_baud0"; >> + interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH 0>; >> + pinctrl-0 = <&uart1_bus>; >> + pinctrl-names = "default"; >> + samsung,uart-fifosize = <256>; >> + status = "disabled"; >> + }; >> + >> cmu_hsi0: clock-controller@10a00000 { >> compatible = "samsung,exynos2200-cmu-hsi0"; >> reg = <0x10a00000 0x8000>; >> @@ -458,6 +471,19 @@ pinctrl_peric2: pinctrl@11c30000 { >> reg = <0x11c30000 0x1000>; >> }; >> >> + serial_0: serial@11c40000 { >> + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; >> + reg = <0x11c40000 0x100>; >> + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, >> + <&cmu_peric2 CLK_DOUT_PERIC2_UART_DBG>; >> + clock-names = "uart", "clk_uart_baud0"; >> + interrupts = <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>; >> + pinctrl-0 = <&uart0_bus_single>; >> + pinctrl-names = "default"; >> + samsung,uart-fifosize = <256>; >> + status = "disabled"; >> + }; >> + > Shouldn't these two serial nodes be children of some corresponding USI > nodes? Which :P > IIUC, the downstream counterpart of this device tree is [1]? I > can see the corresponding USI node is missing there. And if you don't > have the TRM, it might get confusing. But, apart from my intuition > telling me that those UART blocks *should* be implemented as a part of > USI IP blocks in Exynos2200, there is also a fact that the downstream > driver is actually accessing USI registers in exynos_usi_init() > function, in the exynos-uart driver here: [2]. Unless that does nothing and Samsung did not care enough to strip the code for it. > If that's correct, it > means there should exist a USI block, which should be modeled like so: > > 8<------------------------------------------------------------------------->8 > usi_...: usi@11c400c0 { > compatible = ...; > reg = <0x138200c0 0x20>; > samsung,sysreg = <...>; > samsung,mode = <USI_MODE_UART>; > #address-cells = <1>; > #size-cells = <1>; > ranges; > clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, > <&cmu_peric2 CLK_DOUT_PERIC2_UART_DBG>; > clock-names = "pclk", "ipclk"; > status = "disabled"; > > serial_0: serial@11c40000 { > compatible = "samsung,exynos2200-uart", "google,gs101-uart"; > reg = <0x11c40000 0x100>; > clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, > <&cmu_peric2 CLK_DOUT_PERIC2_UART_DBG>; > clock-names = "uart", "clk_uart_baud0"; > interrupts = <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH 0>; > pinctrl-0 = <&uart0_bus_single>; > pinctrl-names = "default"; > samsung,uart-fifosize = <256>; > status = "disabled"; > }; > }; > 8<------------------------------------------------------------------------->8 > > This way you can achieve the same behavior as in downstream kernel, by > making the (upstream) USI driver to initialize corresponding USI > registers for you. > > Does that make any sense? Not really. Perhaps you could __verify__ to what USI instance it belongs? And is there a sysreg register for controlling the behavior of that? Again, I know nothing more than what downstream says. Best regards, Ivaylo > > Thanks! > > [1] https://github.com/jgudec/android_kernel_samsung_exynos2200/blob/CWAI/arch/arm64/boot/dts/exynos/s5e9925.dts#L4648 > [2] https://github.com/jgudec/android_kernel_samsung_exynos2200/blob/CWAI/drivers/tty/serial/exynos_tty.c#L2181 > > >> cmu_cmgp: clock-controller@14e00000 { >> compatible = "samsung,exynos2200-cmu-cmgp"; >> reg = <0x14e00000 0x8000>; >> -- >> 2.43.0 >> >> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 5/5] arm64: dts: exynos2200: define all usi nodes 2025-07-30 7:42 [PATCH v2 0/5] arm64: dts: exynos2200: introduce serial busses, except spi Ivaylo Ivanov ` (3 preceding siblings ...) 2025-07-30 7:42 ` [PATCH v2 4/5] arm64: dts: exynos2200: add serial_0/1 nodes Ivaylo Ivanov @ 2025-07-30 7:42 ` Ivaylo Ivanov 2025-08-02 0:29 ` Sam Protsenko 4 siblings, 1 reply; 14+ messages in thread From: Ivaylo Ivanov @ 2025-07-30 7:42 UTC (permalink / raw) To: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley Cc: linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel Universal Serial Interface (USI) supports three types of serial interfaces - uart, i2c and spi. Each protocol can work independently and configured using external configuration inputs. As each USI instance has access to 4 pins, there are multiple possible configurations: - the first 2 and the last 2 pins can be i2c (sda/scl) or uart (rx/tx) - the 4 pins can be used for 4 pin uart or spi Such configuration can be achieved by setting the mode property of usiX and usiX_i2c nodes correctly - if usiX is set to take up 2 pins, then usiX_i2c can be set to take the other 2. If usiX is set for 4 pins, then usiX_i2c should be left disabled. Define all the USI nodes from peric0 (usi4), peric1 (usi7-10), peric2 (usi0-6, usi11) and cmgp (usi0-6_cmgp, 2 pin usi7_cmgp) blocks, as well as their respective uart and i2c subnodes. As Samsung, for some reason, has decided to restart the counting of usi instances for cmgp, suffix labels for nodes of such with _cmgp. Spi support will be added later on. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> --- arch/arm64/boot/dts/exynos/exynos2200.dtsi | 1361 ++++++++++++++++++++ 1 file changed, 1361 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi index 22c6da907..f83e6cf24 100644 --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/clock/samsung,exynos2200-cmu.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/soc/samsung,exynos-usi.h> / { compatible = "samsung,exynos2200"; @@ -314,6 +315,76 @@ pinctrl_peric0: pinctrl@10430000 { reg = <0x10430000 0x1000>; }; + usi4: usi@105000c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x105000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric0 0x1024>; + status = "disabled"; + + hsi2c_8: i2c@10500000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10500000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_DOUT_PERIC0_USI04>, + <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c8_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_6: serial@10500000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10500000 0xc0>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart6_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi4_i2c: usi@105100c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x105100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric0 CLK_DOUT_PERIC0_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric0 0x1024>; + status = "disabled"; + + hsi2c_9: i2c@10510000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10510000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric0 CLK_DOUT_PERIC0_I2C>, + <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c9_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + cmu_peric1: clock-controller@10700000 { compatible = "samsung,exynos2200-cmu-peric1"; reg = <0x10700000 0x8000>; @@ -349,6 +420,287 @@ serial_1: serial@10840000 { status = "disabled"; }; + usi7: usi@109000c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric1 0x2030>; + status = "disabled"; + + hsi2c_14: i2c@10900000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10900000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI07>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_9: serial@10900000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10900000 0xc0>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart9_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi7_i2c: usi@109100c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI07_SPI_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric1 0x2034>; + status = "disabled"; + + hsi2c_15: i2c@10910000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10910000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI07_SPI_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c15_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi8: usi@109200c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric1 0x2038>; + status = "disabled"; + + hsi2c_16: i2c@10920000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10920000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI08>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c16_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_10: serial@10920000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10920000 0xc0>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart10_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi8_i2c: usi@109300c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI08_SPI_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric1 0x203c>; + status = "disabled"; + + hsi2c_17: i2c@10930000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10930000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI08_SPI_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c17_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi9: usi@109400c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI09>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric1 0x2040>; + status = "disabled"; + + hsi2c_18: i2c@10940000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10940000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI09>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c18_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_11: serial@10940000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10940000 0xc0>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI09>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart11_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi9_i2c: usi@109500c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric1 0x2044>; + status = "disabled"; + + hsi2c_19: i2c@10950000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10950000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c19_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi10: usi@109600c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI10>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric1 0x2048>; + status = "disabled"; + + hsi2c_20: i2c@10960000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10960000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_USI10>, + <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c20_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_12: serial@10960000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x10960000 0xc0>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC1_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_USI10>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart12_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi10_i2c: usi@109700c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x109700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>, + <&cmu_peric1 CLK_DOUT_PERIC1_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric1 0x204c>; + status = "disabled"; + + hsi2c_21: i2c@10970000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x10970000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric1 CLK_DOUT_PERIC1_I2C>, + <&cmu_peric1 CLK_MOUT_PERIC0_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c21_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + }; + cmu_hsi0: clock-controller@10a00000 { compatible = "samsung,exynos2200-cmu-hsi0"; reg = <0x10a00000 0x8000>; @@ -484,6 +836,496 @@ serial_0: serial@11c40000 { status = "disabled"; }; + usi0: usi@11d000c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x2000>; + status = "disabled"; + + hsi2c_0: i2c@11d00000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d00000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI00>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c0_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_2: serial@11d00000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11d00000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart2_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi0_i2c: usi@11d100c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI00_SPI_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x2004>; + status = "disabled"; + + hsi2c_1: i2c@11d10000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d10000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI00_SPI_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c1_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi1: usi@11d200c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x2008>; + status = "disabled"; + + hsi2c_2: i2c@11d20000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d20000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI01>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c2_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_3: serial@11d20000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11d20000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart3_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi1_i2c: usi@11d300c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI01_SPI_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x200c>; + status = "disabled"; + + hsi2c_3: i2c@11d30000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d30000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI01_SPI_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c3_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi2: usi@11d400c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI02>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x2010>; + status = "disabled"; + + hsi2c_4: i2c@11d40000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d40000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI02>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c4_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_4: serial@11d40000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11d40000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI02>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart4_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi2_i2c: usi@11d500c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x2014>; + status = "disabled"; + + hsi2c_5: i2c@11d50000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d50000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi3: usi@11d600c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI03>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x2018>; + status = "disabled"; + + hsi2c_6: i2c@11d60000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d60000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI03>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_5: serial@11d60000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11d60000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI03>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart5_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi3_i2c: usi@11d700c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x201c>; + status = "disabled"; + + hsi2c_7: i2c@11d70000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d70000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c7_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi5_i2c: usi@11d800c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d800c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x102c>; + status = "disabled"; + + hsi2c_11: i2c@11d80000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d80000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c11_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi6_i2c: usi@11d900c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11d900c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x1004>; + status = "disabled"; + + hsi2c_13: i2c@11d90000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11d90000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c13_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi11: usi@11da00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11da00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI11>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x1058>; + status = "disabled"; + + hsi2c_22: i2c@11da0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11da0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI11>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c22_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_13: serial@11da0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11da0000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI11>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart13_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi11_i2c: usi@11db00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11db00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_peric2 0x105c>; + status = "disabled"; + + hsi2c_23: i2c@11db0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11db0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_I2C>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c23_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi5: usi@11dd00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11dd00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI05>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x117c>; + status = "disabled"; + + hsi2c_10: i2c@11dd0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11dd0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI05>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_7: serial@11dd0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11dd0000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI05>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart7_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <256>; + status = "disabled"; + }; + }; + + usi6: usi@11de00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x11de00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI06>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_peric2 0x1180>; + status = "disabled"; + + hsi2c_12: i2c@11de0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x11de0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peric2 CLK_DOUT_PERIC2_USI06>, + <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_8: serial@11de0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x11de0000 0xc0>; + clocks = <&cmu_peric2 CLK_MOUT_PERIC2_NOC_USER>, + <&cmu_peric2 CLK_DOUT_PERIC2_USI06>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart8_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + cmu_cmgp: clock-controller@14e00000 { compatible = "samsung,exynos2200-cmu-cmgp"; reg = <0x14e00000 0x8000>; @@ -511,6 +1353,525 @@ wakeup-interrupt-controller { }; }; + usi0_cmgp: usi@14f000c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f000c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI0>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2000>; + status = "disabled"; + + hsi2c_24: i2c@14f00000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f00000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI0>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c24_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_14: serial@14f00000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f00000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI0>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart14_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi0_i2c_cmgp: usi@14f100c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f100c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C0>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2070>; + status = "disabled"; + + hsi2c_25: i2c@14f10000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f10000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C0>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c25_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi1_cmgp: usi@14f200c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f200c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI1>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2010>; + status = "disabled"; + + hsi2c_26: i2c@14f20000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f20000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI1>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c26_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_15: serial@14f20000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f20000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI1>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart15_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi1_i2c_cmgp: usi@14f300c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f300c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C1>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2074>; + status = "disabled"; + + hsi2c_27: i2c@14f30000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f30000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_SPI_I2C1>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c27_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi2_cmgp: usi@14f400c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f400c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI2>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2020>; + status = "disabled"; + + hsi2c_28: i2c@14f40000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f40000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI2>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c28_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_16: serial@14f40000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f40000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI2>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart16_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi2_i2c_cmgp: usi@14f500c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f500c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2024>; + status = "disabled"; + + hsi2c_29: i2c@14f50000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f50000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c29_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi3_cmgp: usi@14f600c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f600c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI3>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2030>; + status = "disabled"; + + hsi2c_30: i2c@14f60000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f60000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI3>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c30_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_17: serial@14f60000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f60000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI3>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart17_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi3_i2c_cmgp: usi@14f700c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f700c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2034>; + status = "disabled"; + + hsi2c_31: i2c@14f70000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f70000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c31_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi4_cmgp: usi@14f800c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f800c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI4>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2040>; + status = "disabled"; + + hsi2c_32: i2c@14f80000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f80000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI4>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c32_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_18: serial@14f80000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14f80000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI4>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart18_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi4_i2c_cmgp: usi@14f900c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14f900c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2044>; + status = "disabled"; + + hsi2c_33: i2c@14f90000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14f90000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c33_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi5_cmgp: usi@14fa00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fa00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI5>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2050>; + status = "disabled"; + + hsi2c_34: i2c@14fa0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fa0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI5>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c34_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_19: serial@14fa0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14fa0000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI5>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart19_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi5_i2c_cmgp: usi@14fb00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fb00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2054>; + status = "disabled"; + + hsi2c_35: i2c@14fb0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fb0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c35_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi6_cmgp: usi@14fc00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fc00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI6>; + clock-names = "pclk", "ipclk"; + samsung,sysreg = <&syscon_cmgp 0x2060>; + status = "disabled"; + + hsi2c_36: i2c@14fc0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fc0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_USI6>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c36_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_20: serial@14fc0000 { + compatible = "samsung,exynos2200-uart", "google,gs101-uart"; + reg = <0x14fc0000 0xc0>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_USI6>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&uart20_bus_single>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + }; + + usi6_i2c_cmgp: usi@14fd00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fd00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2064>; + status = "disabled"; + + hsi2c_37: i2c@14fd0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fd0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c37_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi7_i2c_cmgp: usi@14fe00c0 { + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; + reg = <0x14fe00c0 0x20>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>, + <&cmu_cmgp CLK_DOUT_CMGP_I2C>; + clock-names = "pclk", "ipclk"; + samsung,mode = <USI_MODE_I2C>; + samsung,sysreg = <&syscon_cmgp 0x2080>; + status = "disabled"; + + hsi2c_38: i2c@14fe0000 { + compatible = "samsung,exynos2200-hsi2c", + "samsung,exynosautov9-hsi2c"; + reg = <0x14fe0000 0xc0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_cmgp CLK_DOUT_CMGP_I2C>, + <&cmu_cmgp CLK_MOUT_CMGP_CLKALIVE_NOC_USER>; + clock-names = "hsi2c", "hsi2c_pclk"; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-0 = <&hsi2c38_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + cmu_vts: clock-controller@15300000 { compatible = "samsung,exynos2200-cmu-vts"; reg = <0x15300000 0x8000>; -- 2.43.0 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/5] arm64: dts: exynos2200: define all usi nodes 2025-07-30 7:42 ` [PATCH v2 5/5] arm64: dts: exynos2200: define all usi nodes Ivaylo Ivanov @ 2025-08-02 0:29 ` Sam Protsenko 2025-08-06 13:57 ` Ivaylo Ivanov 0 siblings, 1 reply; 14+ messages in thread From: Sam Protsenko @ 2025-08-02 0:29 UTC (permalink / raw) To: Ivaylo Ivanov Cc: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley, linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel On Wed, Jul 30, 2025 at 2:44 AM Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> wrote: > > Universal Serial Interface (USI) supports three types of serial > interfaces - uart, i2c and spi. Each protocol can work independently > and configured using external configuration inputs. > > As each USI instance has access to 4 pins, there are multiple possible > configurations: > - the first 2 and the last 2 pins can be i2c (sda/scl) or uart (rx/tx) > - the 4 pins can be used for 4 pin uart or spi > > Such configuration can be achieved by setting the mode property of usiX > and usiX_i2c nodes correctly - if usiX is set to take up 2 pins, then > usiX_i2c can be set to take the other 2. If usiX is set for 4 pins, then > usiX_i2c should be left disabled. > The whole naming scheme is a bit confusing: one might think that because both usiX and usiX_i2c have the same number (X), they represent the same USI block. I can see how they might share the same pins, but it doesn't seem enough to me to justify this convention. If I'm missing something, please help me understand why it should be done like that? > Define all the USI nodes from peric0 (usi4), peric1 (usi7-10), peric2 > (usi0-6, usi11) and cmgp (usi0-6_cmgp, 2 pin usi7_cmgp) blocks, as well > as their respective uart and i2c subnodes. As Samsung, for some reason, > has decided to restart the counting of usi instances for cmgp, suffix > labels for nodes of such with _cmgp. > Yeah, they probably meant to number CMGP instances, not USI instances. Because CMGP (stands for Common GPIO) is actually a separate IP block containing: - 2 x USIs - 1 GPIO controller (8 GPIO lines) - One general purpose ADC - 6 interrupt combiners So some USI blocks are separate USIs, and some USI blocks are a part of bigger CMGP blocks. And instead of using "usi_01_cmgp" for example, they should've gone with "usi_cmgp01". Usually it's recommended to follow the naming scheme from the TRM, but AFAIU you don't have one. And the scheme used in the downstream device tree looks like comlete garbage. Anyways, I don't have strong preference on the naming scheme. Frankly I'd just do the consecutive numbering for all the USI nodes in this case, like: usi0, usi1, etc. And add the comments when needed, like "USI from CMGP01 block". > Spi support will be added later on. > > Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> > --- > arch/arm64/boot/dts/exynos/exynos2200.dtsi | 1361 ++++++++++++++++++++ > 1 file changed, 1361 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi > index 22c6da907..f83e6cf24 100644 > --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi > @@ -7,6 +7,7 @@ > > #include <dt-bindings/clock/samsung,exynos2200-cmu.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/soc/samsung,exynos-usi.h> > > / { > compatible = "samsung,exynos2200"; > @@ -314,6 +315,76 @@ pinctrl_peric0: pinctrl@10430000 { > reg = <0x10430000 0x1000>; > }; > > + usi4: usi@105000c0 { > + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; > + reg = <0x105000c0 0x20>; > + ranges; > + #address-cells = <1>; > + #size-cells = <1>; > + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, > + <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; > + clock-names = "pclk", "ipclk"; > + samsung,sysreg = <&syscon_peric0 0x1024>; > + status = "disabled"; > + > + hsi2c_8: i2c@10500000 { Why not number all the underlying protocol nodes using the same number as the USI node? Like it's done in gs101.dtsi. And maybe even follow USI naming scheme used in gs101 in general? Like, sort all USI nodes by unit address, and then number them starting from 0. If some other USIs are missing (like I mentioned in my review for the previous patch), add those too, first. [snip] ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v2 5/5] arm64: dts: exynos2200: define all usi nodes 2025-08-02 0:29 ` Sam Protsenko @ 2025-08-06 13:57 ` Ivaylo Ivanov 0 siblings, 0 replies; 14+ messages in thread From: Ivaylo Ivanov @ 2025-08-06 13:57 UTC (permalink / raw) To: Sam Protsenko Cc: Krzysztof Kozlowski, Alim Akhtar, Rob Herring, Conor Dooley, linux-samsung-soc, devicetree, linux-arm-kernel, linux-kernel On 8/2/25 03:29, Sam Protsenko wrote: > On Wed, Jul 30, 2025 at 2:44 AM Ivaylo Ivanov > <ivo.ivanov.ivanov1@gmail.com> wrote: >> Universal Serial Interface (USI) supports three types of serial >> interfaces - uart, i2c and spi. Each protocol can work independently >> and configured using external configuration inputs. >> >> As each USI instance has access to 4 pins, there are multiple possible >> configurations: >> - the first 2 and the last 2 pins can be i2c (sda/scl) or uart (rx/tx) >> - the 4 pins can be used for 4 pin uart or spi >> >> Such configuration can be achieved by setting the mode property of usiX >> and usiX_i2c nodes correctly - if usiX is set to take up 2 pins, then >> usiX_i2c can be set to take the other 2. If usiX is set for 4 pins, then >> usiX_i2c should be left disabled. >> > The whole naming scheme is a bit confusing: one might think that > because both usiX and usiX_i2c have the same number (X), they > represent the same USI block. Mapped to a different address? Hm, I doubt. > I can see how they might share the same > pins, but it doesn't seem enough to me to justify this convention. If > I'm missing something, please help me understand why it should be done > like that? That's the way it was done by Samsung in downstream, and specifically in upstream for autov9 [1]. Clocks are already merged and definitions expect the convention implied by my patch. Iit'll be way more mangled if we use non-matching node to header-definition names. > >> Define all the USI nodes from peric0 (usi4), peric1 (usi7-10), peric2 >> (usi0-6, usi11) and cmgp (usi0-6_cmgp, 2 pin usi7_cmgp) blocks, as well >> as their respective uart and i2c subnodes. As Samsung, for some reason, >> has decided to restart the counting of usi instances for cmgp, suffix >> labels for nodes of such with _cmgp. >> > Yeah, they probably meant to number CMGP instances, not USI instances. > Because CMGP (stands for Common GPIO) is actually a separate IP block > containing: > - 2 x USIs > - 1 GPIO controller (8 GPIO lines) > - One general purpose ADC > - 6 interrupt combiners > > So some USI blocks are separate USIs, and some USI blocks are a part > of bigger CMGP blocks. And instead of using "usi_01_cmgp" for example, > they should've gone with "usi_cmgp01". I guess. > > Usually it's recommended to follow the naming scheme from the TRM, but > AFAIU you don't have one. Yes... > And the scheme used in the downstream device > tree looks like comlete garbage. Anyways, I don't have strong > preference on the naming scheme. Frankly I'd just do the consecutive > numbering for all the USI nodes in this case, like: usi0, usi1, etc. > And add the comments when needed, like "USI from CMGP01 block". This will mangle stuff way too much for my preference. People will be way more confused when comparing this to the downstream device tree too, as the average Jo does not have access to anything apart from kernel source (like me -_-). > >> Spi support will be added later on. >> >> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> >> --- >> arch/arm64/boot/dts/exynos/exynos2200.dtsi | 1361 ++++++++++++++++++++ >> 1 file changed, 1361 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/exynos/exynos2200.dtsi b/arch/arm64/boot/dts/exynos/exynos2200.dtsi >> index 22c6da907..f83e6cf24 100644 >> --- a/arch/arm64/boot/dts/exynos/exynos2200.dtsi >> +++ b/arch/arm64/boot/dts/exynos/exynos2200.dtsi >> @@ -7,6 +7,7 @@ >> >> #include <dt-bindings/clock/samsung,exynos2200-cmu.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/soc/samsung,exynos-usi.h> >> >> / { >> compatible = "samsung,exynos2200"; >> @@ -314,6 +315,76 @@ pinctrl_peric0: pinctrl@10430000 { >> reg = <0x10430000 0x1000>; >> }; >> >> + usi4: usi@105000c0 { >> + compatible = "samsung,exynos2200-usi", "samsung,exynos850-usi"; >> + reg = <0x105000c0 0x20>; >> + ranges; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>, >> + <&cmu_peric0 CLK_DOUT_PERIC0_USI04>; >> + clock-names = "pclk", "ipclk"; >> + samsung,sysreg = <&syscon_peric0 0x1024>; >> + status = "disabled"; >> + >> + hsi2c_8: i2c@10500000 { > Why not number all the underlying protocol nodes using the same number > as the USI node? Same as above, my wild guess is that Samsung ordered them by physical position. Best regards, Ivaylo [1] https://github.com/torvalds/linux/blob/cca7a0aae8958c9b1cd14116cb8b2f22ace2205e/arch/arm64/boot/dts/exynos/exynosautov9.dtsi#L503 > Like it's done in gs101.dtsi. And maybe even follow > USI naming scheme used in gs101 in general? Like, sort all USI nodes > by unit address, and then number them starting from 0. If some other > USIs are missing (like I mentioned in my review for the previous > patch), add those too, first. > > [snip] ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2025-08-06 14:05 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-07-30 7:42 [PATCH v2 0/5] arm64: dts: exynos2200: introduce serial busses, except spi Ivaylo Ivanov 2025-07-30 7:42 ` [PATCH v2 1/5] arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label Ivaylo Ivanov 2025-08-01 20:59 ` Sam Protsenko 2025-07-30 7:42 ` [PATCH v2 2/5] arm64: dts: exynos2200: use 32-bit address space for /soc Ivaylo Ivanov 2025-08-01 21:16 ` Sam Protsenko 2025-07-30 7:42 ` [PATCH v2 3/5] arm64: dts: exynos2200: increase peric1 and cmgp syscon sizes Ivaylo Ivanov 2025-08-01 22:11 ` Sam Protsenko 2025-08-06 14:05 ` Ivaylo Ivanov 2025-07-30 7:42 ` [PATCH v2 4/5] arm64: dts: exynos2200: add serial_0/1 nodes Ivaylo Ivanov 2025-08-01 23:12 ` Sam Protsenko 2025-08-06 14:03 ` Ivaylo Ivanov 2025-07-30 7:42 ` [PATCH v2 5/5] arm64: dts: exynos2200: define all usi nodes Ivaylo Ivanov 2025-08-02 0:29 ` Sam Protsenko 2025-08-06 13:57 ` Ivaylo Ivanov
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