From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A865C4167B for ; Tue, 27 Dec 2022 13:04:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231535AbiL0NEO (ORCPT ); Tue, 27 Dec 2022 08:04:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49210 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229789AbiL0NEO (ORCPT ); Tue, 27 Dec 2022 08:04:14 -0500 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9A5D6551 for ; Tue, 27 Dec 2022 05:04:12 -0800 (PST) Received: by mail-lf1-x12d.google.com with SMTP id g13so19524047lfv.7 for ; Tue, 27 Dec 2022 05:04:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=qzvnqvpfZxu7B6kg0qSsGJfAG0LQru6+OuRh723noP4=; b=lcM8TBfDGcFAIkWxg1oXJFAveTT1wDlhgbYoRMHLM32fkuXuk5cwJ0MwcnPOzaJQn9 yPX4grQok8/rcQrLNHb2ItB7WyWFo/9dH8dUAzGsG0U1CjToL+ZNgEXWy2pJoCK6cL9i L5EEcP0qeiEkZe83BYl2OyVLNMS1UZfTy52faJ2s3vaJDBgx8WHYlp1/gXb381fpjRrw i/p89WkmiWpUtc4mCXxsSma2uWk/t4h70H5zFARfL7jJz+p5v3EWS+zQLpJtDATFr9bG x/BNmRKqR5HY/DqQsStLRHNMjo9hpOEvBWJw7qF9sLOGdecv6//4eMEwNR/QNyh7K4iR 7vHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=qzvnqvpfZxu7B6kg0qSsGJfAG0LQru6+OuRh723noP4=; b=geRWOSl2HhClXL2u3zubnqi4pFLe6fipl7Yyrqt9UjO60ItHNbtrfashH7bjWx4ffO uM3Sh1yadA326FY4WH1HahU0LLlGFlGLUkzfc9+if+8jGhRBrMB5g5X/e3XA1ns3xYqI AyrqMBdI1TCUPIAA1CQ9oL1Ai4Cf3jVAv+zzC+G/hAMFMCXUx5JAl1P3SNTj1i+hW1CL eW5E5Cq52vvpnfhMI6Ncd1D6Z7l+Gr7csYC48PiHtNFHMZ2y9Mwzzy1RDEWdALPtpho0 cVhRFhlz9XG2vsd6OaXpav8AUok9PM7cDHv0gy6i7pit2QCWot3BvSthoxmt98+RTvR8 FAvA== X-Gm-Message-State: AFqh2krssvZW2yH2R90Gxqv+A+TIlW3xqhI2v6IzhFA2CBP87DfrA/oD +ju1v7tYnyegXVqQrKtZYNcMyA== X-Google-Smtp-Source: AMrXdXvY7JMniZ9MhKJxM4RFSmwoLcWJ7DaLanG9fsVliw3zc2taRQ0iQ2th+W2Ktkt0tTyWoOfSdg== X-Received: by 2002:ac2:5ec9:0:b0:4b5:b6e8:bb53 with SMTP id d9-20020ac25ec9000000b004b5b6e8bb53mr5742473lfq.24.1672146250976; Tue, 27 Dec 2022 05:04:10 -0800 (PST) Received: from [192.168.1.101] (abyl184.neoplus.adsl.tpnet.pl. [83.9.31.184]) by smtp.gmail.com with ESMTPSA id be33-20020a056512252100b004b56de48f05sm2221142lfb.27.2022.12.27.05.04.08 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Dec 2022 05:04:10 -0800 (PST) Message-ID: Date: Tue, 27 Dec 2022 14:04:07 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [RFC PATCH 12/12] ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device Content-Language: en-US To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20221227013225.2847382-1-dmitry.baryshkov@linaro.org> <20221227013225.2847382-13-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 27.12.2022 13:31, Dmitry Baryshkov wrote: > On Tue, 27 Dec 2022 at 14:08, Konrad Dybcio wrote: >> >> >> >> On 27.12.2022 02:32, Dmitry Baryshkov wrote: >>> Add clocks and clock-names nodes to the gcc device to bind clocks using >>> the DT links. >>> >>> Signed-off-by: Dmitry Baryshkov >>> --- >> Reviewed-by: Konrad Dybcio >> >> Though - again at the end of reviewing - I noticed you could have >> gone .index instead, like with qcs404. > > QCS404 driver was in a good shape, so I doubt there will be any > significant changes for the bindings. On the other hand the apq8084 is > in such a flux state, that I can easily imagine getting additional > clock parents and/or removing existing parents. This can better be > coped with by using the clock-names instead of indices. For example, > see my comment regarding the pcie pipe clocks. I fear that apq8084 was > not seriously touched for the last 5 years. And even back in those > days not everything was plumbed together. None of MMCC (and thus > display, camera, venus), SATA, PCIe are present in the > qcom-apq8084.dtsi. Sure, sounds reasonable! Konrad > >> >> Konrad >> >>> arch/arm/boot/dts/qcom-apq8084.dtsi | 18 ++++++++++++++++++ >>> 1 file changed, 18 insertions(+) >>> >>> diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi >>> index fe30abfff90a..815b6c53f7b8 100644 >>> --- a/arch/arm/boot/dts/qcom-apq8084.dtsi >>> +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi >>> @@ -388,6 +388,24 @@ gcc: clock-controller@fc400000 { >>> #reset-cells = <1>; >>> #power-domain-cells = <1>; >>> reg = <0xfc400000 0x4000>; >>> + clocks = <&xo_board>, >>> + <&sleep_clk>, >>> + <0>, /* ufs */ >>> + <0>, >>> + <0>, >>> + <0>, >>> + <0>, /* sata */ >>> + <0>, >>> + <0>; /* pcie */ >>> + clock-names = "xo", >>> + "sleep_clk", >>> + "ufs_rx_symbol_0_clk_src", >>> + "ufs_rx_symbol_1_clk_src", >>> + "ufs_tx_symbol_0_clk_src", >>> + "ufs_tx_symbol_1_clk_src", >>> + "sata_asic0_clk", >>> + "sata_rx_clk", >>> + "pcie_pipe"; >>> }; >>> >>> tcsr_mutex: hwlock@fd484000 { > > >