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Mon, 26 Oct 2026 08:01:55 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c46bd4e89cesm335488366b.13.2026.10.26.08.01.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 26 Oct 2026 08:01:53 -0700 (PDT) Message-ID: Date: Mon, 26 Oct 2026 16:01:49 +0100 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 5/7] arm64: dts: qcom: Add initial support for MSM8952 To: muzafferkadir@mainlining.org, Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Abel Vesa , Kees Cook , Tony Luck , "Guilherme G. Piccoli" , Dmitry Torokhov Cc: David Heidelberg , phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, iommu@lists.linux.dev, linux-pm@vger.kernel.org, linux-input@vger.kernel.org References: <20261011-msm8952-initial-support-v5-0-1857074992ec@mainlining.org> <20261011-msm8952-initial-support-v5-5-1857074992ec@mainlining.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261011-msm8952-initial-support-v5-5-1857074992ec@mainlining.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI2MDA1OSBTYWx0ZWRfXzM4WkWCQ8Z4P UN3efCM6fApi0PN9tIuR6Tk6FUwXaK/ojvUurdChBB14oCJ9Grp3NS3UWNosb0OLMzE+KarRFqF BKSVn8APCaV5nFZVCbWtxwIqqFMWi6I= X-Proofpoint-GUID: NZio0lpPc-lQXu4hAE5XZCnJq-WwndV5 X-Authority-Analysis: v=2.4 cv=c+8+0h9l c=1 sm=1 tr=0 ts=6adf6b65 cx=c_pps a=UbhLPJ621ZpgOD2l3yZY1w==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=OuZLqq7tAAAA:8 a=FRBEkmYdsRQmicOyHakA:9 a=QEXdDO2ut3YA:10 a=TOPH6uDL9cOC6tEoww4z:22 a=AKGiAy9iJ-JzxKVHQNES:22 X-Proofpoint-ORIG-GUID: NZio0lpPc-lQXu4hAE5XZCnJq-WwndV5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI2MDA1OSBTYWx0ZWRfXw5JFncZiewnR 5hPLDJeFLM9sOBgx71x3K5jfGKmo47o8/XW/P/6V3q2fpb27moGwHyo+s73fdskgTJWYyftzkCk nBRQXyS/5q+eerj0F/HHa+C8+Rjds6/74SNT44v7gLjd2+00o6uqV6zNVd9Oop24DwxY01IXlW6 ye2M7YrptjP94Z0vVmOXFe0zDxohL5PGIqbr3QPWd2/cSpVcVEKFlaHyRi90x559JgG91RkGpEf 2XgngYLbG78Zw4bhBesgC5m4AwV6acbXyCXR861YzTIdyR0t8Au5mau8d0eLuJDduJucFNBUfqC 5ZvwhGm+4FgnkVDbFMsKSsOEH4ghEuqL7+HQNqK1mLUf9CmvNk+TKVUE9MY14EXjUok9AI9NeST vHwer6TaGsqi/xffxKEiTn461zsQ47stMlvfyAh7+TgOGbyH0eLmUHGWs4h2MbasQXSdg8hIfg/ 70k/BJw7Fs+9FMkntHg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-26_03,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 adultscore=0 phishscore=0 impostorscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610260059 On 10/11/26 6:51 PM, Muzaffer Kadir via B4 Relay wrote: > From: Muzaffer Kadir > > Add initial support for MSM8952 SoC. > > AI help is used for calculating qfprom nodes. > > Downstream reference for port is [1] which is very lightly modified > version of [2]. Generally this looks good, couple more comments [...] > + soc: soc@0 { > + compatible = "simple-bus"; > + ranges = <0 0 0 0xffffffff>; this is equal to `ranges;` [...] > + sdhc_1: mmc@7824900 { > + compatible = "qcom,msm8952-sdhci", "qcom,sdhci-msm-v4"; > + reg = <0x07824900 0x500>, <0x07824000 0x800>, <0x7824e00 0x200>; > + reg-names = "hc", "core", "cqhci"; Please break up these into one-per-line (also for properties below) the last reg entry needs a leading zero (in general one-per-line is cool) [...] > + usb: usb@78db000 { > + compatible = "qcom,ci-hdrc"; > + reg = <0x078db000 0x200>, > + <0x078db200 0x200>; > + interrupts-extended = <&mpm 58 IRQ_TYPE_LEVEL_HIGH>, > + <&mpm 49 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_USB_HS_AHB_CLK>, > + <&gcc GCC_USB_HS_SYSTEM_CLK>; > + clock-names = "iface", > + "core"; > + assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; > + assigned-clock-rates = <80000000>; > + resets = <&gcc GCC_USB_HS_BCR>; > + reset-names = "core"; > + hnp-disable; > + srp-disable; > + adp-disable; > + ahb-burst-config = <0>; > + dr_mode = "otg"; dr_mode = otg is default - you can drop it [...] > + pll_opp_table_c1: opp-table { > + compatible = "operating-points-v2"; > + > + opp-499200000 { > + opp-hz = /bits/ 64 <499200000>; > + }; > + > + opp-806400000 { > + opp-hz = /bits/ 64 <806400000>; > + }; > + > + opp-960000000 { > + opp-hz = /bits/ 64 <960000000>; > + }; > + > + opp-1094400000 { > + opp-hz = /bits/ 64 <1094400000>; > + }; > + > + opp-1344000000 { > + opp-hz = /bits/ 64 <1344000000>; > + }; > + > + opp-1440000000 { > + opp-hz = /bits/ 64 <1440000000>; > + }; > + > + opp-1516800000 { > + opp-hz = /bits/ 64 <1516800000>; > + }; > + > + opp-1651200000 { > + opp-hz = /bits/ 64 <1651200000>; > + }; Drop the last entry for the same reasons you explained [...] > + a53pll_cci: clock@b1d0000 { > + compatible = "qcom,msm8939-a53pll"; This needs a 8952-specific compatible (bindings-only fallback is fine) > + reg = <0x0b1d0000 0x40>; > + clocks = <&xo_board>; > + clock-names = "xo"; > + #clock-cells = <0>; > + }; > + > + apcs2: mailbox@b1d1000 { > + compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; Likewise > + reg = <0x0b1d1000 0x1000>; > + clocks = <&a53pll_cci>, > + <&gcc GPLL0_VOTE>, > + <&rpmcc RPM_SMD_XO_CLK_SRC>; > + clock-names = "pll", > + "aux", > + "ref"; > + #clock-cells = <0>; > + #mbox-cells = <1>; > + }; > + > + adsp: remoteproc@c200000 { > + compatible = "qcom,msm8996-adsp-pil"; And likewise also IMEM, DSI, RPMPD, RPMCC [...] > + thermal-zones { > + aoss0-thermal { > + polling-delay-passive = <250>; TSENS sensors are interrupt-driven so you don't need polling AOSS is surely the wrong name - that hw didn't come until years later than 8952 was released. I can't find a mapping of the sensors for this SoC right now, so either drop these or give them some generic names [...] > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; > + clock-frequency = <19200000>; Drop this property, it's only needed for very broken FWs Konrad