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[83.9.2.167]) by smtp.gmail.com with ESMTPSA id n17-20020a2e8791000000b002b6ca937d60sm2487484lji.8.2023.07.15.05.36.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 15 Jul 2023 05:36:20 -0700 (PDT) Message-ID: Date: Sat, 15 Jul 2023 14:36:18 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v4 4/6] arm64: dts: qcom: ipq5332: Add USB related nodes Content-Language: en-US To: Varadarajan Narayanan , agross@kernel.org, andersson@kernel.org, vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, gregkh@linuxfoundation.org, catalin.marinas@arm.com, will@kernel.org, p.zabel@pengutronix.de, arnd@arndb.de, geert+renesas@glider.be, neil.armstrong@linaro.org, nfraprado@collabora.com, rafal@milecki.pl, quic_srichara@quicinc.com, quic_varada@quicinc.org, quic_wcheng@quicinc.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org References: <1f99805b6437aa8d6eaa4663e8d27b98ee595f00.1689160067.git.quic_varada@quicinc.com> From: Konrad Dybcio In-Reply-To: <1f99805b6437aa8d6eaa4663e8d27b98ee595f00.1689160067.git.quic_varada@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 12.07.2023 13:38, Varadarajan Narayanan wrote: > Add USB phy and controller nodes. > > Signed-off-by: Varadarajan Narayanan > --- > v4: > Change node name > Remove blank line > 'make CHECK_DTBS=y DT_SCHEMA_FILES=qcom qcom/ipq5332-rdp441.dtb' passed DT_SCHEMA_FILES accepts yaml files Konrad > v1: > Rename phy node > Change compatible from m31,ipq5332-usb-hsphy -> qcom,ipq5332-usb-hsphy > Remove 'qscratch' from phy node > Fix alignment and upper-case hex no.s > Add clock definition for the phy > Remove snps,ref-clock-period-ns as it is not used. dwc3_ref_clk_period() > in dwc3/core.c takes the frequency from ref clock and calculates fladj > as appropriate. > --- > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 53 +++++++++++++++++++++++++++++++++++ > 1 file changed, 53 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > index 8bfc2db..8118356 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > @@ -405,6 +405,59 @@ > status = "disabled"; > }; > }; > + > + usbphy0: usb-phy@7b000 { > + compatible = "qcom,ipq5332-usb-hsphy"; > + reg = <0x0007b000 0x12c>; > + > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; > + clock-names = "cfg_ahb"; > + > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > + > + status = "disabled"; > + }; > + > + usb2: usb2@8a00000 { > + compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; > + reg = <0x08af8800 0x400>; > + > + interrupts = ; > + interrupt-names = "hs_phy_irq"; > + > + clocks = <&gcc GCC_USB0_MASTER_CLK>, > + <&gcc GCC_SNOC_USB_CLK>, > + <&gcc GCC_USB0_SLEEP_CLK>, > + <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + clock-names = "core", > + "iface", > + "sleep", > + "mock_utmi"; > + > + resets = <&gcc GCC_USB_BCR>; > + > + qcom,select-utmi-as-pipe-clk; > + > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; > + > + status = "disabled"; > + > + usb2_0_dwc: usb@8a00000 { > + compatible = "snps,dwc3"; > + reg = <0x08a00000 0xe000>; > + clocks = <&gcc GCC_USB0_MOCK_UTMI_CLK>; > + clock-names = "ref"; > + interrupts = ; > + usb-phy = <&usbphy0>; > + tx-fifo-resize; > + snps,is-utmi-l1-suspend; > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_u3_susphy_quirk; > + }; > + }; > }; > > timer {