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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dc73c2e00sm12529611f8f.57.2025.02.11.02.22.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Feb 2025 02:22:13 -0800 (PST) Message-ID: Date: Tue, 11 Feb 2025 11:22:13 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/6] RISC-V: add f & d extension validation checks To: Conor Dooley , linux-riscv@lists.infradead.org Cc: Conor Dooley , Eric Biggers , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250205-cobbler-unpadded-5580c1f5d946@spud> <20250205-stifle-remake-4e497e96fd66@spud> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: <20250205-stifle-remake-4e497e96fd66@spud> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 05/02/2025 17:05, Conor Dooley wrote: > From: Conor Dooley > > Using Clement's new validation callbacks, support checking that > dependencies have been satisfied for the floating point extensions. > > The check for "d" might be slightly confusingly shorter than that of "f", > despite "d" depending on "f". This is because the requirement that a > hart supporting double precision must also support single precision, > should be validated by dt-bindings etc, not the kernel but lack of > support for single precision only is a limitation of the kernel. > > Since vector will now be disabled proactively, there's no need to clear > the bit in elf_hwcap in riscv_fill_hwcap() any longer. > > Signed-off-by: Conor Dooley > --- > arch/riscv/kernel/cpufeature.c | 27 +++++++++++++++++++++++++-- > 1 file changed, 25 insertions(+), 2 deletions(-) > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 1c148ecea612..ad4fbaa4ff0d 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -109,6 +109,29 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data, > return 0; > } > > +static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data, > + const unsigned long *isa_bitmap) > +{ > + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) { > + pr_warn_once("This kernel does not support systems with F but not D\n"); > + return -EINVAL; > + } While I tested to remove the RISCV_ISA_EXT_d from the input isa bitmap and it worked, I didn't realized that it was due to the probe order of single letter extensions. D is probed before F so that works as expected. But returning -EPROBEDEFER would not allow to display the warn_once or wrongly display it if D was not yet probed. So I'm inclined to keep it as is and rely on probe order (a bit fragile but for single letter extensions, that seems acceptable). > + > + if (!IS_ENABLED(CONFIG_FPU)) > + return -EINVAL; I would have actually move that chunk before the __riscv_isa_extension_available() check so that the whole function body is elided if FPU is disabled. Clément > + > + return 0; > +} > + > +static int riscv_ext_d_validate(const struct riscv_isa_ext_data *data, > + const unsigned long *isa_bitmap) > +{ > + if (!IS_ENABLED(CONFIG_FPU)) > + return -EINVAL; > + > + return 0; > +} > + > static int riscv_ext_vector_x_validate(const struct riscv_isa_ext_data *data, > const unsigned long *isa_bitmap) > { > @@ -368,8 +391,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), > __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), > __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a), > - __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), > - __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), > + __RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_f, riscv_ext_f_validate), > + __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate), > __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), > __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), > __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv_ext_vector_float_validate),