* [PATCH v2 1/8] clk: add device tree binding for artpec-6 pll1 clock
2016-02-11 14:04 [PATCH v2 0/8] arm: Add Artpec-6 SoC Lars Persson
@ 2016-02-11 14:04 ` Lars Persson
2016-02-11 14:04 ` [PATCH v2 2/8] clk: add artpec-6 pll1 clock driver Lars Persson
` (7 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Lars Persson @ 2016-02-11 14:04 UTC (permalink / raw)
To: linux-arm-kernel, devicetree, linux-clk
Cc: mark.rutland, pawel.moll, ijc+devicetree, Lars Persson,
linux-kernel, robh+dt, galak
Add device tree documentation for the main PLL in the Artpec-6 SoC.
Signed-off-by: Lars Persson <larper@axis.com>
---
Documentation/devicetree/bindings/clock/artpec6.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/artpec6.txt
diff --git a/Documentation/devicetree/bindings/clock/artpec6.txt b/Documentation/devicetree/bindings/clock/artpec6.txt
new file mode 100644
index 0000000..521fec8
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/artpec6.txt
@@ -0,0 +1,16 @@
+* Clock bindings for Axis ARTPEC-6 chip
+
+Required properties:
+- #clock-cells: Should be <0>
+- compatible: Should be "axis,artpec6-pll1-clock"
+- reg: Address and length of the DEVSTAT register.
+- clocks: The PLL's input clock.
+
+Examples:
+
+pll1_clk: pll1_clk {
+ #clock-cells = <0>;
+ compatible = "axis,artpec6-pll1-clock";
+ reg = <0xf8000000 4>;
+ clocks = <&ext_clk>;
+};
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 2/8] clk: add artpec-6 pll1 clock driver
2016-02-11 14:04 [PATCH v2 0/8] arm: Add Artpec-6 SoC Lars Persson
2016-02-11 14:04 ` [PATCH v2 1/8] clk: add device tree binding for artpec-6 pll1 clock Lars Persson
@ 2016-02-11 14:04 ` Lars Persson
2016-02-11 14:04 ` [PATCH v2 3/8] arm: add device-tree SoC bindings for Axis Artpec-6 Lars Persson
` (6 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Lars Persson @ 2016-02-11 14:04 UTC (permalink / raw)
To: linux-arm-kernel, devicetree, linux-clk
Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linux-kernel, Lars Persson
The PLL1 clock is a fixed-factor clock with factors derived from boot
mode pins. This driver is a simple wrapper to register the fixed
factor clock according to the pin settings.
Signed-off-by: Lars Persson <larper@axis.com>
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-artpec6.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 71 insertions(+)
create mode 100644 drivers/clk/clk-artpec6.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index b038e36..388f0cf 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -17,6 +17,7 @@ endif
# hardware specific clock types
# please keep this section sorted lexicographically by file/directory path name
+obj-$(CONFIG_MACH_ARTPEC6) += clk-artpec6.o
obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o
diff --git a/drivers/clk/clk-artpec6.c b/drivers/clk/clk-artpec6.c
new file mode 100644
index 0000000..3664c44
--- /dev/null
+++ b/drivers/clk/clk-artpec6.c
@@ -0,0 +1,70 @@
+/*
+ * ARTPEC-6 clock initialization
+ *
+ * Copyright 2015 Axis Comunications AB.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+static void __init of_artpec6_pll1_setup(struct device_node *np)
+{
+ void __iomem *devstat;
+ struct clk *clk;
+ const char *clk_name = np->name;
+ const char *parent_name;
+ u32 pll_mode, pll_m, pll_n;
+
+ parent_name = of_clk_get_parent_name(np, 0);
+
+ devstat = of_iomap(np, 0);
+ if (devstat == NULL) {
+ pr_err("error to ioremap DEVSTAT\n");
+ return;
+ }
+
+ /* DEVSTAT register contains PLL settings */
+ pll_mode = (readl(devstat) >> 6) & 3;
+ iounmap(devstat);
+
+ /*
+ * pll1 settings are designed for different DDR speeds using a fixed
+ * 50MHz external clock. However, a different external clock could be
+ * used on different boards.
+ * CPU clock is half the DDR clock.
+ */
+ switch (pll_mode) {
+ case 0: /* DDR3-2133 mode */
+ pll_m = 4;
+ pll_n = 85;
+ break;
+ case 1: /* DDR3-1866 mode */
+ pll_m = 6;
+ pll_n = 112;
+ break;
+ case 2: /* DDR3-1600 mode */
+ pll_m = 4;
+ pll_n = 64;
+ break;
+ case 3: /* DDR3-1333 mode */
+ pll_m = 8;
+ pll_n = 106;
+ break;
+ }
+ /* ext_clk is defined in device tree */
+ clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
+ pll_n, pll_m);
+ if (IS_ERR(clk)) {
+ pr_err("%s not registered\n", clk_name);
+ return;
+ }
+ of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+CLK_OF_DECLARE(artpec6_pll1, "axis,artpec6-pll1-clock", of_artpec6_pll1_setup);
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 3/8] arm: add device-tree SoC bindings for Axis Artpec-6
2016-02-11 14:04 [PATCH v2 0/8] arm: Add Artpec-6 SoC Lars Persson
2016-02-11 14:04 ` [PATCH v2 1/8] clk: add device tree binding for artpec-6 pll1 clock Lars Persson
2016-02-11 14:04 ` [PATCH v2 2/8] clk: add artpec-6 pll1 clock driver Lars Persson
@ 2016-02-11 14:04 ` Lars Persson
2016-02-11 14:14 ` Arnd Bergmann
2016-02-11 14:04 ` [PATCH v2 4/8] arm: dts: add Artpec-6 SoC dtsi file Lars Persson
` (5 subsequent siblings)
8 siblings, 1 reply; 11+ messages in thread
From: Lars Persson @ 2016-02-11 14:04 UTC (permalink / raw)
To: linux-arm-kernel, devicetree, linux-clk
Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linux-kernel, Lars Persson
This adds device tree bindings for the Artpec-6 SoC.
Signed-off-by: Lars Persson <larper@axis.com>
---
Documentation/devicetree/bindings/arm/axis.txt | 29 ++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/axis.txt
diff --git a/Documentation/devicetree/bindings/arm/axis.txt b/Documentation/devicetree/bindings/arm/axis.txt
new file mode 100644
index 0000000..203a305
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/axis.txt
@@ -0,0 +1,29 @@
+Axis Communications AB
+ARTPEC series SoC Device Tree Bindings
+
+ARTPEC-6 ARM SoC
+================
+
+Required root node properties:
+- compatible = "axis,artpec6";
+
+ARTPEC-6 DMA Configuration
+--------------------------
+
+The DMA configuration unit muxes dma request lines between single and burst
+alternatives.
+
+Required properties:
+- compatible: axis,artpec6-dmacfg
+- reg: Address and length of DMACFG register.
+
+Example:
+ dmacfg {
+ compatible = "axis,artpec6-dmacfg";
+ reg = <0xf8000010 4>;
+ };
+
+ARTPEC-6 Development board:
+---------------------------
+Required root node properties:
+- compatible = "axis,artpec6-dev-board", "axis,artpec6";
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v2 3/8] arm: add device-tree SoC bindings for Axis Artpec-6
2016-02-11 14:04 ` [PATCH v2 3/8] arm: add device-tree SoC bindings for Axis Artpec-6 Lars Persson
@ 2016-02-11 14:14 ` Arnd Bergmann
0 siblings, 0 replies; 11+ messages in thread
From: Arnd Bergmann @ 2016-02-11 14:14 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Lars Persson, devicetree, linux-clk, mark.rutland, pawel.moll,
ijc+devicetree, Lars Persson, linux-kernel, robh+dt, galak
On Thursday 11 February 2016 15:04:37 Lars Persson wrote:
> +
> +The DMA configuration unit muxes dma request lines between single and burst
> +alternatives.
> +
> +Required properties:
> +- compatible: axis,artpec6-dmacfg
> +- reg: Address and length of DMACFG register.
> +
> +Example:
> + dmacfg {
> + compatible = "axis,artpec6-dmacfg";
> + reg = <0xf8000010 4>;
> + };
> +
This method looks better than before, but putting a single register
into DT looks wrong. I can almost guarantee that there are more
registers at 0xf8000000-0xf8000fff (or more) that belong to either
some system controller or a DMA controller.
Whatever it is, please describe it in the DT in a sensible way based
on what the hardware does and what other resources it uses (interrupts
etc) rather than what today's kernel happens to need.
Arnd
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 4/8] arm: dts: add Artpec-6 SoC dtsi file
2016-02-11 14:04 [PATCH v2 0/8] arm: Add Artpec-6 SoC Lars Persson
` (2 preceding siblings ...)
2016-02-11 14:04 ` [PATCH v2 3/8] arm: add device-tree SoC bindings for Axis Artpec-6 Lars Persson
@ 2016-02-11 14:04 ` Lars Persson
[not found] ` <cover.1455198819.git.larper-VrBV9hrLPhE@public.gmane.org>
` (4 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Lars Persson @ 2016-02-11 14:04 UTC (permalink / raw)
To: linux-arm-kernel, devicetree, linux-clk
Cc: mark.rutland, pawel.moll, ijc+devicetree, Lars Persson,
linux-kernel, robh+dt, galak
Initial device tree for the Artpec-6 SoC.
Signed-off-by: Lars Persson <larper@axis.com>
---
arch/arm/boot/dts/artpec6.dtsi | 236 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 236 insertions(+)
create mode 100644 arch/arm/boot/dts/artpec6.dtsi
diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
new file mode 100644
index 0000000..8b28f72
--- /dev/null
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -0,0 +1,236 @@
+/*
+ * Device Tree Source for the Axis ARTPEC-6 SoC
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "axis,artpec6";
+ interrupt-parent = <&intc>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ next-level-cache = <&pl310>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ next-level-cache = <&pl310>;
+ };
+ };
+
+ dmacfg {
+ compatible = "axis,artpec6-dmacfg";
+ reg = <0xf8000010 4>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2", "arm,psci";
+ method = "smc";
+ psci_version = <0x84000000>;
+ cpu_on = <0x84000003>;
+ system_reset = <0x84000009>;
+ };
+
+ scu@faf00000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xfaf00000 0x58>;
+ };
+
+ /* Main external clock driving CPU and peripherals */
+ ext_clk: ext_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ };
+
+ /* PLL1 is used by CPU and some peripherals */
+ pll1_clk: pll1_clk@f8000000 {
+ #clock-cells = <0>;
+ compatible = "axis,artpec6-pll1-clock";
+ reg = <0xf8000000 4>;
+ clocks = <&ext_clk>;
+ };
+
+ cpu_clk: cpu_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <1>;
+ clock-mult = <1>;
+ clocks = <&pll1_clk>;
+ clock-output-names = "cpu_clk";
+ };
+
+ cpu_clkdiv2: cpu_clkdiv2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&cpu_clk>;
+ };
+
+ cpu_clkdiv4: cpu_clkdiv4 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <4>;
+ clock-mult = <1>;
+ clocks = <&cpu_clk>;
+ };
+
+ apb_pclk: apb_pclk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <8>;
+ clock-mult = <1>;
+ clocks = <&cpu_clk>;
+ clock-output-names = "apb_pclk";
+ };
+
+ /* PLL2 is used by a number of peripherals, including UDL */
+ pll2: pll2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <1>;
+ clock-mult = <24>;
+ clocks = <&ext_clk>;
+ };
+
+ /* PLL2DIV2 is used by the Fractional Clock Divider, for i2s */
+ pll2div2: pll2div2 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <2>;
+ clock-mult = <1>;
+ clocks = <&pll2>;
+ };
+
+ pll2div12: pll2div12 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <12>;
+ clock-mult = <1>;
+ clocks = <&pll2>;
+ };
+
+ pll2div24: pll2div24 {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clock-div = <24>;
+ clock-mult = <1>;
+ clocks = <&pll2>;
+ clock-output-names = "uart_clk";
+ };
+
+
+ gtimer@faf00200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xfaf00200 0x20>;
+ interrupts = <GIC_PPI 11 0xf01>;
+ clocks = <&cpu_clkdiv2>;
+ };
+
+ timer@faf00600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0xfaf00600 0x20>;
+ interrupts = <GIC_PPI 13 0xf04>;
+ clocks = <&cpu_clkdiv2>;
+ status = "disabled";
+ };
+
+ intc: interrupt-controller@faf01000 {
+ interrupt-controller;
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
+ };
+
+ pl310: cache-controller@faf10000 {
+ compatible = "arm,pl310-cache";
+ cache-unified;
+ cache-level = <2>;
+ reg = <0xfaf10000 0x1000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ arm,data-latency = <1 1 1>;
+ arm,tag-latency = <1 1 1>;
+ arm,filter-ranges = <0x0 0x80000000>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+ };
+
+ amba@0 {
+ compatible = "simple-bus";
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ interrupt-parent = <&intc>;
+ ranges;
+ dma-ranges = <0x80000000 0x00000000 0x40000000>;
+ dma-coherent;
+
+ ethernet: ethernet@f8010000 {
+ clock-names = "phy_ref_clk", "apb_pclk";
+ clocks = <&ext_clk>, <&apb_pclk>;
+ compatible = "snps,dwc-qos-ethernet-4.10";
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf8010000 0x4000>;
+
+ snps,write-requests = <2>;
+ snps,read-requests = <16>;
+ snps,txpbl = <8>;
+ snps,rxpbl = <2>;
+
+ status = "disabled";
+ };
+
+ uart0: serial@f8036000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0xf8036000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pll2div24>, <&apb_pclk>;
+ clock-names = "uart_clk", "apb_pclk";
+ status = "disabled";
+ };
+ uart1: serial@f8037000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0xf8037000 0x1000>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pll2div24>, <&apb_pclk>;
+ clock-names = "uart_clk", "apb_pclk";
+ status = "disabled";
+ };
+ uart2: serial@f8038000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0xf8038000 0x1000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pll2div24>, <&apb_pclk>;
+ clock-names = "uart_clk", "apb_pclk";
+ status = "disabled";
+ };
+ uart3: serial@f8039000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0xf8039000 0x1000>;
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pll2div24>, <&apb_pclk>;
+ clock-names = "uart_clk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread[parent not found: <cover.1455198819.git.larper-VrBV9hrLPhE@public.gmane.org>]
* [PATCH v2 5/8] arm: dts: add Artpec-6 development board dts
[not found] ` <cover.1455198819.git.larper-VrBV9hrLPhE@public.gmane.org>
@ 2016-02-11 14:04 ` Lars Persson
0 siblings, 0 replies; 11+ messages in thread
From: Lars Persson @ 2016-02-11 14:04 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Lars Persson
Signed-off-by: Lars Persson <larper-VrBV9hrLPhE@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 2 ++
arch/arm/boot/dts/artpec6-devboard.dts | 64 ++++++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
create mode 100644 arch/arm/boot/dts/artpec6-devboard.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a4a6d70..2ebe99c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -2,6 +2,8 @@ ifeq ($(CONFIG_OF),y)
dtb-$(CONFIG_ARCH_ALPINE) += \
alpine-db.dtb
+dtb-$(CONFIG_MACH_ARTPEC6) += \
+ artpec6-devboard.dtb
dtb-$(CONFIG_MACH_ASM9260) += \
alphascale-asm9260-devkit.dtb
# Keep at91 dtb files sorted alphabetically for each SoC
diff --git a/arch/arm/boot/dts/artpec6-devboard.dts b/arch/arm/boot/dts/artpec6-devboard.dts
new file mode 100644
index 0000000..f823ed3
--- /dev/null
+++ b/arch/arm/boot/dts/artpec6-devboard.dts
@@ -0,0 +1,64 @@
+/*
+ * Axis ARTPEC-6 development board.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "artpec6.dtsi"
+
+/ {
+ model = "ARTPEC-6 development board";
+ compatible = "axis,artpec6-dev-board", "axis,artpec6";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ };
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+ðernet {
+ status = "okay";
+
+ phy-handle = <&phy1>;
+ phy-mode = "gmii";
+
+ mdio {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ phy1: phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ device_type = "ethernet-phy";
+ reg = <0x0>;
+ };
+ };
+};
--
2.1.4
--
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 6/8] arm: initial machine port for artpec-6 SoC
2016-02-11 14:04 [PATCH v2 0/8] arm: Add Artpec-6 SoC Lars Persson
` (4 preceding siblings ...)
[not found] ` <cover.1455198819.git.larper-VrBV9hrLPhE@public.gmane.org>
@ 2016-02-11 14:04 ` Lars Persson
2016-02-11 14:04 ` [PATCH v2 7/8] arm: multi_v7_defconfig: add MACH_ARTPEC6 Lars Persson
` (2 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Lars Persson @ 2016-02-11 14:04 UTC (permalink / raw)
To: linux-arm-kernel, devicetree, linux-clk
Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
linux-kernel, Lars Persson
Basic machine port for the Artpec-6 SoC from Axis
Communications.
Signed-off-by: Lars Persson <larper@axis.com>
---
arch/arm/Kconfig | 2 +
arch/arm/Makefile | 1 +
arch/arm/mach-artpec/Kconfig | 20 ++++++++++
arch/arm/mach-artpec/Makefile | 1 +
arch/arm/mach-artpec/board-artpec6.c | 72 ++++++++++++++++++++++++++++++++++++
5 files changed, 96 insertions(+)
create mode 100644 arch/arm/mach-artpec/Kconfig
create mode 100644 arch/arm/mach-artpec/Makefile
create mode 100644 arch/arm/mach-artpec/board-artpec6.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4f799e5..e1565dd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -724,6 +724,8 @@ source "arch/arm/mach-mvebu/Kconfig"
source "arch/arm/mach-alpine/Kconfig"
+source "arch/arm/mach-artpec/Kconfig"
+
source "arch/arm/mach-asm9260/Kconfig"
source "arch/arm/mach-at91/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index fe25410..4eb24c6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -154,6 +154,7 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
machine-$(CONFIG_ARCH_ALPINE) += alpine
+machine-$(CONFIG_ARCH_ARTPEC) += artpec
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_AXXIA) += axxia
machine-$(CONFIG_ARCH_BCM) += bcm
diff --git a/arch/arm/mach-artpec/Kconfig b/arch/arm/mach-artpec/Kconfig
new file mode 100644
index 0000000..6cbe5a2
--- /dev/null
+++ b/arch/arm/mach-artpec/Kconfig
@@ -0,0 +1,20 @@
+menuconfig ARCH_ARTPEC
+ bool "Axis Communications ARM based ARTPEC SoCs"
+ depends on ARCH_MULTI_V7
+
+if ARCH_ARTPEC
+
+config MACH_ARTPEC6
+ bool "Axis ARTPEC-6 ARM Cortex A9 Platform"
+ depends on ARCH_MULTI_V7
+ select ARM_AMBA
+ select ARM_GIC
+ select ARM_GLOBAL_TIMER
+ select ARM_PSCI
+ select HAVE_ARM_ARCH_TIMER
+ select HAVE_ARM_SCU
+ select HAVE_ARM_TWD if SMP
+ help
+ Support for Axis ARTPEC-6 ARM Cortex A9 Platform
+
+endif
diff --git a/arch/arm/mach-artpec/Makefile b/arch/arm/mach-artpec/Makefile
new file mode 100644
index 0000000..78325f0
--- /dev/null
+++ b/arch/arm/mach-artpec/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MACH_ARTPEC6) := board-artpec6.o
diff --git a/arch/arm/mach-artpec/board-artpec6.c b/arch/arm/mach-artpec/board-artpec6.c
new file mode 100644
index 0000000..d486217
--- /dev/null
+++ b/arch/arm/mach-artpec/board-artpec6.c
@@ -0,0 +1,72 @@
+/*
+ * ARTPEC-6 device support.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/amba/bus.h>
+#include <linux/clocksource.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/of_platform.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk-provider.h>
+#include <linux/smp.h>
+#include <asm/smp_scu.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/psci.h>
+#include <linux/arm-smccc.h>
+
+#define ARTPEC6_DMACFG_UARTS_BURST 0xff
+
+#define SECURE_OP_L2C_WRITEREG 0xb4000001
+
+static void __init artpec6_init_machine(void)
+{
+ void __iomem *dmacfg;
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "axis,artpec6-dmacfg");
+ if (np) {
+ /* Use PL011 DMA Burst Request signal instead of DMA
+ * Single Request
+ */
+ dmacfg = of_iomap(np, 0);
+ BUG_ON(!dmacfg);
+
+ writel(ARTPEC6_DMACFG_UARTS_BURST, dmacfg);
+ iounmap(dmacfg);
+ of_node_put(np);
+ };
+
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+}
+
+static void artpec6_l2c310_write_sec(unsigned long val, unsigned reg)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(SECURE_OP_L2C_WRITEREG, reg, val, 0,
+ 0, 0, 0, 0, &res);
+
+ WARN_ON(res.a0);
+}
+
+static const char * const artpec6_dt_match[] = {
+ "axis,artpec6",
+ NULL
+};
+
+DT_MACHINE_START(ARTPEC6, "Axis ARTPEC-6 Platform")
+ .l2c_aux_val = 0x0C000000,
+ .l2c_aux_mask = 0xF3FFFFFF,
+ .l2c_write_sec = artpec6_l2c310_write_sec,
+ .init_machine = artpec6_init_machine,
+ .dt_compat = artpec6_dt_match,
+MACHINE_END
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 7/8] arm: multi_v7_defconfig: add MACH_ARTPEC6
2016-02-11 14:04 [PATCH v2 0/8] arm: Add Artpec-6 SoC Lars Persson
` (5 preceding siblings ...)
2016-02-11 14:04 ` [PATCH v2 6/8] arm: initial machine port for artpec-6 SoC Lars Persson
@ 2016-02-11 14:04 ` Lars Persson
2016-02-11 14:04 ` [PATCH v2 8/8] arm: mach-artpec: add entry to MAINTAINERS Lars Persson
2016-02-11 14:17 ` [PATCH v2 0/8] arm: Add Artpec-6 SoC Arnd Bergmann
8 siblings, 0 replies; 11+ messages in thread
From: Lars Persson @ 2016-02-11 14:04 UTC (permalink / raw)
To: linux-arm-kernel, devicetree, linux-clk
Cc: mark.rutland, pawel.moll, ijc+devicetree, Lars Persson,
linux-kernel, robh+dt, galak
Signed-off-by: Lars Persson <larper@axis.com>
---
arch/arm/configs/multi_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 8e8b2ac..1149642 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -16,6 +16,8 @@ CONFIG_ARCH_MULTI_V7=y
# CONFIG_ARCH_MULTI_V4 is not set
CONFIG_ARCH_VIRT=y
CONFIG_ARCH_ALPINE=y
+CONFIG_ARCH_ARTPEC=y
+CONFIG_MACH_ARTPEC6=y
CONFIG_ARCH_MVEBU=y
CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_375=y
@@ -227,6 +229,7 @@ CONFIG_R8169=y
CONFIG_SH_ETH=y
CONFIG_SMSC911X=y
CONFIG_STMMAC_ETH=y
+CONFIG_SYNOPSYS_DWC_ETH_QOS=y
CONFIG_TI_CPSW=y
CONFIG_XILINX_EMACLITE=y
CONFIG_AT803X_PHY=y
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v2 8/8] arm: mach-artpec: add entry to MAINTAINERS
2016-02-11 14:04 [PATCH v2 0/8] arm: Add Artpec-6 SoC Lars Persson
` (6 preceding siblings ...)
2016-02-11 14:04 ` [PATCH v2 7/8] arm: multi_v7_defconfig: add MACH_ARTPEC6 Lars Persson
@ 2016-02-11 14:04 ` Lars Persson
2016-02-11 14:17 ` [PATCH v2 0/8] arm: Add Artpec-6 SoC Arnd Bergmann
8 siblings, 0 replies; 11+ messages in thread
From: Lars Persson @ 2016-02-11 14:04 UTC (permalink / raw)
To: linux-arm-kernel, devicetree, linux-clk
Cc: mark.rutland, pawel.moll, ijc+devicetree, Lars Persson,
linux-kernel, Jesper Nilsson, robh+dt, galak
Signed-off-by: Lars Persson <larper@axis.com>
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
---
MAINTAINERS | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7f1fa4f..d32c1aa 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -932,6 +932,16 @@ M: Tsahee Zidenberg <tsahee@annapurnalabs.com>
S: Maintained
F: arch/arm/mach-alpine/
+ARM/ARTPEC MACHINE SUPPORT
+M: Jesper Nilsson <jesper.nilsson@axis.com>
+M: Lars Persson <lars.persson@axis.com>
+M: Niklas Cassel <niklas.cassel@axis.com>
+S: Maintained
+L: linux-arm-kernel@axis.com
+F: arch/arm/mach-artpec
+F: arch/arm/boot/dts/artpec6*
+F: drivers/clk/clk-artpec6.c
+
ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT
M: Nicolas Ferre <nicolas.ferre@atmel.com>
M: Alexandre Belloni <alexandre.belloni@free-electrons.com>
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v2 0/8] arm: Add Artpec-6 SoC
2016-02-11 14:04 [PATCH v2 0/8] arm: Add Artpec-6 SoC Lars Persson
` (7 preceding siblings ...)
2016-02-11 14:04 ` [PATCH v2 8/8] arm: mach-artpec: add entry to MAINTAINERS Lars Persson
@ 2016-02-11 14:17 ` Arnd Bergmann
8 siblings, 0 replies; 11+ messages in thread
From: Arnd Bergmann @ 2016-02-11 14:17 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Lars Persson, devicetree, linux-clk, mark.rutland, pawel.moll,
ijc+devicetree, Lars Persson, linux-kernel, robh+dt, galak
On Thursday 11 February 2016 15:04:34 Lars Persson wrote:
> Basic support for the Axis Artpec-6 ARM SoC. Timers, interrupts, UARTs and
> ethernet are wired up.
>
> Changes since v1:
> - Corrected bindings for axis,artpec6-pll1-clock.
> - Moved the uart aliases to the board dts.
> - Kconfig cleanup.
> - Added a device tree binding for the dma configuration.
> - Added CONFIG_SYNOPSYS_DWC_ETH_QOS to multi_v7_defconfig.
> - Added binding documentation for axis,artpec6-dev-board.
>
> Lars Persson (8):
> clk: add device tree binding for artpec-6 pll1 clock
> clk: add artpec-6 pll1 clock driver
> arm: add device-tree SoC bindings for Axis Artpec-6
> arm: dts: add Artpec-6 SoC dtsi file
> arm: dts: add Artpec-6 development board dts
> arm: initial machine port for artpec-6 SoC
> arm: multi_v7_defconfig: add MACH_ARTPEC6
> arm: mach-artpec: add entry to MAINTAINERS
Looks good except for the one issue I pointed out in patch 3 (and also 6).
Once that is resolved, please submit the new platform for inclusion by sending
it to arm@kernel.org.
The first two patches should get merged through the drivers/clk maintainer tree,
please submit them separately there.
Arnd
^ permalink raw reply [flat|nested] 11+ messages in thread