[PATCH v3 0/8] drm/tilcdc: Address LCDC rev 2 color errata + other fixes

[PATCH v3 0/8] drm/tilcdc: Address LCDC rev 2 color errata + other fixes

[Jyri Sarha]

Changes since v2:
- Fiddle with color wiring propety once more, now it follows this Tomi's
  comment:
  - No property set: driver advertises RG16 and RG24. This is
    wrong, but that's what the current status is, right?
  - Property set to "default" or "straight" or whatever: driver
    says RG16 and BG24
  - Property set to "crossed": driver says BG16 and RG24
- Add v2 version of "drm/tilcdc: Write DMA base and ceiling address with..."
  - The first version was sent individually, this second version has
    __iowmb(); and __cpu_to_le64(); added to tilcdc_write64()

Changes since v1:
- Change the blue-and-red-wiring property to boolean blue-and-red-crossed
  - This breaks to little backward compatibility the earlier series had, but
    makes the binding more straight forward
  - This changes requires changes to am335x-evm and am335x-evmsk dts-files
  - The old beaglebone-black dts files remain compatible, but the patch
    suggests in commenst on how to support 24-bit RGB mode with BBB

The first patch ("drm/tilcdc: Remove drm_helper_disable_unused_functions()
call") is completely independent fix.

The red and blue components are reversed between 24 and 16 bit modes
on am335x LCDC output pins. To get 24 RGB format the wires red and
blue wires has to be crossed and this in turn causes 16 colors output
to be in BGR format. With straight wiring the 16 color is RGB and 24
bit is BGR. These patches try to deal with the issue in reasonable
manner.

For more details see section 3.1.1 in AM335x Silicon Errata:
http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360

Jyri Sarha (8):
  drm/tilcdc: Remove drm_helper_disable_unused_functions() call
  drm/tilcdc: Write DMA base and ceiling address with single instruction
  drm/tilcdc: Add blue-and-red-crossed devicetree property
  drm/tilcdc: Choose console BPP that supports RGB
  ARM: dts: am335x-boneblack: Add blue-and-red-wiring -property to LCDC
    node
  ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node
  ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes
  ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node

 .../devicetree/bindings/display/tilcdc/tilcdc.txt  | 22 ++++++++
 arch/arm/boot/dts/am335x-boneblack.dts             | 11 ++++
 arch/arm/boot/dts/am335x-evm.dts                   |  2 +
 arch/arm/boot/dts/am335x-evmsk.dts                 | 42 ++++++++--------
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c               |  9 +++-
 drivers/gpu/drm/tilcdc/tilcdc_drv.c                | 58 ++++++++++++++++++----
 drivers/gpu/drm/tilcdc/tilcdc_drv.h                |  5 +-
 drivers/gpu/drm/tilcdc/tilcdc_external.c           |  7 ++-
 drivers/gpu/drm/tilcdc/tilcdc_external.h           |  2 +-
 drivers/gpu/drm/tilcdc/tilcdc_panel.c              |  2 -
 drivers/gpu/drm/tilcdc/tilcdc_plane.c              |  9 ++--
 drivers/gpu/drm/tilcdc/tilcdc_regs.h               | 14 ++++++
 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c             |  2 -
 13 files changed, 136 insertions(+), 49 deletions(-)

-- 
1.9.1

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[PATCH v3 1/8] drm/tilcdc: Remove drm_helper_disable_unused_functions() call

[Jyri Sarha]

drm_helper_disable_unused_functions() should not be called by atomic
drivers.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 drivers/gpu/drm/tilcdc/tilcdc_drv.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 3404d24..e45c268 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -361,8 +361,6 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags)
 			break;
 	}
 
-	drm_helper_disable_unused_functions(dev);
-
 	drm_mode_config_reset(dev);
 
 	priv->fbdev = drm_fbdev_cma_init(dev, bpp,
-- 
1.9.1

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[PATCH v3 2/8] drm/tilcdc: Write DMA base and ceiling address with single instruction

[Jyri Sarha]

Write DMA base and ceiling address with a single instruction, if
available. This should make it more unlikely that LCDC would fetch the
DMA addresses in the middle of an update. Having bad combination of
addresses in dma base and ceiling (e.g base > ceiling) can cause
unpredictaple behavior in LCDC.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 drivers/gpu/drm/tilcdc/tilcdc_crtc.c |  9 +++++++--
 drivers/gpu/drm/tilcdc/tilcdc_regs.h | 14 ++++++++++++++
 2 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 6350f2a..41ec5b3 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -70,6 +70,7 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
 	struct drm_gem_cma_object *gem;
 	unsigned int depth, bpp;
 	dma_addr_t start, end;
+	u64 dma_base_and_ceiling;
 
 	drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
 	gem = drm_fb_cma_get_gem_obj(fb, 0);
@@ -80,8 +81,12 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
 
 	end = start + (crtc->mode.vdisplay * fb->pitches[0]);
 
-	tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, start);
-	tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, end - 1);
+	/* Write DMA base and ceiling address with a single insruction,
+	 * if available. This should make it more unlikely that LCDC would
+	 * fetch the DMA addresses in the middle of an update.
+	 */
+	dma_base_and_ceiling = (u64)(end - 1) << 32 | start;
+	tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling);
 
 	if (tilcdc_crtc->curr_fb)
 		drm_flip_work_queue(&tilcdc_crtc->unref_work,
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_regs.h b/drivers/gpu/drm/tilcdc/tilcdc_regs.h
index 1bf5e25..61a9c2a 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_regs.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_regs.h
@@ -119,6 +119,20 @@ static inline void tilcdc_write(struct drm_device *dev, u32 reg, u32 data)
 	iowrite32(data, priv->mmio + reg);
 }
 
+static inline void tilcdc_write64(struct drm_device *dev, u32 reg, u64 data)
+{
+	struct tilcdc_drm_private *priv = dev->dev_private;
+	volatile void __iomem *addr = priv->mmio + reg;
+
+#ifdef iowrite64
+	iowrite64(data, addr);
+#else
+	/* This compiles to strd (=64-bit write) on ARM7 */
+	__iowmb();
+	*(volatile u64 __force *)addr = __cpu_to_le64(data);
+#endif
+}
+
 static inline u32 tilcdc_read(struct drm_device *dev, u32 reg)
 {
 	struct tilcdc_drm_private *priv = dev->dev_private;
-- 
1.9.1

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[PATCH v3 3/8] drm/tilcdc: Add blue-and-red-crossed devicetree property

[Jyri Sarha]

Add "blue-and-red-wiring"-device tree property and update devicetree
binding document. The red and blue components are reversed between 24
and 16 bit modes on am335x LCDC output pins. To get 24 RGB format the
red and blue wires has to be crossed and this in turn causes 16 colors
output to be in BGR format. With straight wiring the 16 color is RGB
and 24 bit is BGR. The new property describes whether the red and blue
wires are crossed or not. If the property is not present or its value
is not recognized the legacy mode is assumed. The legacy configuration
supports RGB565, RGB888 and XRGB8888 formats. However, depending on
wiring, the red and blue colors are swapped in either 16 or 24-bit
color modes.

For more details see section 3.1.1 in AM335x Silicon Errata:
http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 .../devicetree/bindings/display/tilcdc/tilcdc.txt  | 22 ++++++++++++
 drivers/gpu/drm/tilcdc/tilcdc_drv.c                | 42 ++++++++++++++++++++++
 drivers/gpu/drm/tilcdc/tilcdc_drv.h                |  4 +++
 drivers/gpu/drm/tilcdc/tilcdc_plane.c              |  9 ++---
 4 files changed, 71 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
index 6efa4c5..5b7b5f8 100644
--- a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
+++ b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
@@ -17,6 +17,18 @@ Optional properties:
    the lcd controller.
  - max-pixelclock: The maximum pixel clock that can be supported
    by the lcd controller in KHz.
+ - blue-and-red-wiring: Recognized values "default", "straight" or
+   "crossed". This property deals with the LCDC revision 2 (found on
+   AM335x) color errata [1].
+     - "default" and "straight" indicates normal wiring that supports
+      RGB565, BGR888, and XBGR8888 color formats.
+    - "crossed" indicates wiring that has blue and red wires
+      crossed. This setup supports BGR565, RGB888 and XRGB8888
+      formats.
+    - If the property is not present or its value is not recognized
+      the legacy mode is assumed. This configuration supports RGB565,
+      RGB888 and XRGB8888 formats. However, depending on wiring, the red
+      and blue colors are swapped in either 16 or 24-bit color modes.
 
 Optional nodes:
 
@@ -28,6 +40,14 @@ Optional nodes:
    Documentation/devicetree/bindings/display/tilcdc/tfp410.txt for connecting
    tfp410 DVI encoder or lcd panel to lcdc
 
+[1] There is an errata about AM335x color wiring. For 16-bit color mode
+    the wires work as they should (LCD_DATA[0:4] is for Blue[3:7]),
+    but for 24 bit color modes the wiring of blue and red components is
+    crossed and LCD_DATA[0:4] is for Red[3:7] and LCD_DATA[11:15] is
+    for Blue[3-7]. For more details see section 3.1.1 in AM335x
+    Silicon Errata:
+    http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
+
 Example:
 
 	fb: fb@4830e000 {
@@ -37,6 +57,8 @@ Example:
 		interrupts = <36>;
 		ti,hwmods = "lcdc";
 
+		blue-and-red-wiring = "crossed";
+
 		port {
 			lcdc_0: endpoint@0 {
 				remote-endpoint = <&hdmi_0>;
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index e45c268..4371537 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -33,6 +33,20 @@
 
 static LIST_HEAD(module_list);
 
+static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
+
+static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
+					       DRM_FORMAT_BGR888,
+					       DRM_FORMAT_XBGR8888 };
+
+static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
+					      DRM_FORMAT_RGB888,
+					      DRM_FORMAT_XRGB8888 };
+
+static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
+					     DRM_FORMAT_RGB888,
+					     DRM_FORMAT_XRGB8888 };
+
 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
 		const struct tilcdc_module_ops *funcs)
 {
@@ -318,6 +332,34 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags)
 
 	pm_runtime_put_sync(dev->dev);
 
+	if (priv->rev == 1) {
+		DBG("Revision 1 LCDC supports only RGB565 format");
+		priv->pixelformats = tilcdc_rev1_formats;
+		priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
+	} else {
+		const char *str = "\0";
+
+		of_property_read_string(node, "blue-and-red-wiring", &str);
+		if (0 == strcmp(str, "crossed")) {
+			DBG("Configured for crossed blue and red wires");
+			priv->pixelformats = tilcdc_crossed_formats;
+			priv->num_pixelformats =
+				ARRAY_SIZE(tilcdc_crossed_formats);
+		} else if(0 == strcmp(str, "default") ||
+			  0 == strcmp(str, "straight")) {
+			DBG("Configured for straight blue and red wires");
+			priv->pixelformats = tilcdc_straight_formats;
+			priv->num_pixelformats =
+				ARRAY_SIZE(tilcdc_straight_formats);
+		} else {
+			DBG("Blue and red wiring '%s' unknown, use legacy mode",
+			    str);
+			priv->pixelformats = tilcdc_legacy_formats;
+			priv->num_pixelformats =
+				ARRAY_SIZE(tilcdc_legacy_formats);
+		}
+	}
+
 	ret = modeset_init(dev);
 	if (ret < 0) {
 		dev_err(dev->dev, "failed to initialize mode setting\n");
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
index 13001df..0e19c14 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
@@ -65,6 +65,10 @@ struct tilcdc_drm_private {
 	 */
 	uint32_t max_width;
 
+	/* Supported pixel formats */
+	const uint32_t *pixelformats;
+	uint32_t num_pixelformats;
+
 	/* The context for pm susped/resume cycle is stored here */
 	struct drm_atomic_state *saved_state;
 
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_plane.c b/drivers/gpu/drm/tilcdc/tilcdc_plane.c
index 41911e3..74c65fa 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_plane.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_plane.c
@@ -24,10 +24,6 @@
 
 #include "tilcdc_drv.h"
 
-static const u32 tilcdc_formats[] = { DRM_FORMAT_RGB565,
-				      DRM_FORMAT_RGB888,
-				      DRM_FORMAT_XRGB8888 };
-
 static struct drm_plane_funcs tilcdc_plane_funcs = {
 	.update_plane	= drm_atomic_helper_update_plane,
 	.disable_plane	= drm_atomic_helper_disable_plane,
@@ -114,12 +110,13 @@ static const struct drm_plane_helper_funcs plane_helper_funcs = {
 int tilcdc_plane_init(struct drm_device *dev,
 		      struct drm_plane *plane)
 {
+	struct tilcdc_drm_private *priv = dev->dev_private;
 	int ret;
 
 	ret = drm_plane_init(dev, plane, 1,
 			     &tilcdc_plane_funcs,
-			     tilcdc_formats,
-			     ARRAY_SIZE(tilcdc_formats),
+			     priv->pixelformats,
+			     priv->num_pixelformats,
 			     true);
 	if (ret) {
 		dev_err(dev->dev, "Failed to initialize plane: %d\n", ret);
-- 
1.9.1

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[PATCH v3 4/8] drm/tilcdc: Choose console BPP that supports RGB

[Jyri Sarha]

Choose console BPP that supports RGB and remove the old fbdev bpp
selection code. LCDC on AM335x has red and blue wires switched between
24 bit and 16 bit colors. If 24 format is wired for RGB colors, the 16
bit format is wired for BGR. drm_fbdev_cma_init() does not currently
like anything else but RGB formats, so we must choose such bytes per
pixel value that supports RGB.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 drivers/gpu/drm/tilcdc/tilcdc_drv.c      | 14 +++++---------
 drivers/gpu/drm/tilcdc/tilcdc_drv.h      |  1 -
 drivers/gpu/drm/tilcdc/tilcdc_external.c |  7 +++----
 drivers/gpu/drm/tilcdc/tilcdc_external.h |  2 +-
 drivers/gpu/drm/tilcdc/tilcdc_panel.c    |  2 --
 drivers/gpu/drm/tilcdc/tilcdc_tfp410.c   |  2 --
 6 files changed, 9 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.c b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
index 4371537..9a55ea2 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.c
@@ -240,7 +240,6 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags)
 	struct platform_device *pdev = dev->platformdev;
 	struct device_node *node = pdev->dev.of_node;
 	struct tilcdc_drm_private *priv;
-	struct tilcdc_module *mod;
 	struct resource *res;
 	u32 bpp = 0;
 	int ret;
@@ -336,6 +335,7 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags)
 		DBG("Revision 1 LCDC supports only RGB565 format");
 		priv->pixelformats = tilcdc_rev1_formats;
 		priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
+		bpp = 16;
 	} else {
 		const char *str = "\0";
 
@@ -345,18 +345,21 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags)
 			priv->pixelformats = tilcdc_crossed_formats;
 			priv->num_pixelformats =
 				ARRAY_SIZE(tilcdc_crossed_formats);
+			bpp = 32; /* Choose bpp with RGB support for fbdef */
 		} else if(0 == strcmp(str, "default") ||
 			  0 == strcmp(str, "straight")) {
 			DBG("Configured for straight blue and red wires");
 			priv->pixelformats = tilcdc_straight_formats;
 			priv->num_pixelformats =
 				ARRAY_SIZE(tilcdc_straight_formats);
+			bpp = 16; /* Choose bpp with RGB support for fbdef */
 		} else {
 			DBG("Blue and red wiring '%s' unknown, use legacy mode",
 			    str);
 			priv->pixelformats = tilcdc_legacy_formats;
 			priv->num_pixelformats =
 				ARRAY_SIZE(tilcdc_legacy_formats);
+			bpp = 16; /* This is just a guess */
 		}
 	}
 
@@ -373,7 +376,7 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags)
 		if (ret < 0)
 			goto fail_mode_config_cleanup;
 
-		ret = tilcdc_add_external_encoders(dev, &bpp);
+		ret = tilcdc_add_external_encoders(dev);
 		if (ret < 0)
 			goto fail_component_cleanup;
 	}
@@ -396,13 +399,6 @@ static int tilcdc_load(struct drm_device *dev, unsigned long flags)
 		goto fail_vblank_cleanup;
 	}
 
-	list_for_each_entry(mod, &module_list, list) {
-		DBG("%s: preferred_bpp: %d", mod->name, mod->preferred_bpp);
-		bpp = mod->preferred_bpp;
-		if (bpp > 0)
-			break;
-	}
-
 	drm_mode_config_reset(dev);
 
 	priv->fbdev = drm_fbdev_cma_init(dev, bpp,
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_drv.h b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
index 0e19c14..a6e5e6d 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_drv.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_drv.h
@@ -116,7 +116,6 @@ struct tilcdc_module {
 	const char *name;
 	struct list_head list;
 	const struct tilcdc_module_ops *funcs;
-	unsigned int preferred_bpp;
 };
 
 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_external.c b/drivers/gpu/drm/tilcdc/tilcdc_external.c
index 849b23e..68e8950 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_external.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_external.c
@@ -52,7 +52,7 @@ static int tilcdc_external_mode_valid(struct drm_connector *connector,
 	return MODE_OK;
 }
 
-static int tilcdc_add_external_encoder(struct drm_device *dev, int *bpp,
+static int tilcdc_add_external_encoder(struct drm_device *dev,
 				       struct drm_connector *connector)
 {
 	struct tilcdc_drm_private *priv = dev->dev_private;
@@ -64,7 +64,6 @@ static int tilcdc_add_external_encoder(struct drm_device *dev, int *bpp,
 	/* Only tda998x is supported at the moment. */
 	tilcdc_crtc_set_simulate_vesa_sync(priv->crtc, true);
 	tilcdc_crtc_set_panel_info(priv->crtc, &panel_info_tda998x);
-	*bpp = panel_info_tda998x.bpp;
 
 	connector_funcs = devm_kzalloc(dev->dev, sizeof(*connector_funcs),
 				       GFP_KERNEL);
@@ -94,7 +93,7 @@ static int tilcdc_add_external_encoder(struct drm_device *dev, int *bpp,
 	return 0;
 }
 
-int tilcdc_add_external_encoders(struct drm_device *dev, int *bpp)
+int tilcdc_add_external_encoders(struct drm_device *dev)
 {
 	struct tilcdc_drm_private *priv = dev->dev_private;
 	struct drm_connector *connector;
@@ -108,7 +107,7 @@ int tilcdc_add_external_encoders(struct drm_device *dev, int *bpp)
 			if (connector == priv->connectors[i])
 				found = true;
 		if (!found) {
-			ret = tilcdc_add_external_encoder(dev, bpp, connector);
+			ret = tilcdc_add_external_encoder(dev, connector);
 			if (ret)
 				return ret;
 		}
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_external.h b/drivers/gpu/drm/tilcdc/tilcdc_external.h
index 6aabe27..c700e0c 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_external.h
+++ b/drivers/gpu/drm/tilcdc/tilcdc_external.h
@@ -18,7 +18,7 @@
 #ifndef __TILCDC_EXTERNAL_H__
 #define __TILCDC_EXTERNAL_H__
 
-int tilcdc_add_external_encoders(struct drm_device *dev, int *bpp);
+int tilcdc_add_external_encoders(struct drm_device *dev);
 void tilcdc_remove_external_encoders(struct drm_device *dev);
 int tilcdc_get_external_components(struct device *dev,
 				   struct component_match **match);
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_panel.c b/drivers/gpu/drm/tilcdc/tilcdc_panel.c
index 4ac1d25..7b36509 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_panel.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_panel.c
@@ -397,8 +397,6 @@ static int panel_probe(struct platform_device *pdev)
 		goto fail_timings;
 	}
 
-	mod->preferred_bpp = panel_mod->info->bpp;
-
 	return 0;
 
 fail_timings:
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
index 3faf735..6e64a4f 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_tfp410.c
@@ -329,8 +329,6 @@ static int tfp410_probe(struct platform_device *pdev)
 		goto fail;
 	}
 
-	mod->preferred_bpp = dvi_info.bpp;
-
 	i2c_node = of_find_node_by_phandle(i2c_phandle);
 	if (!i2c_node) {
 		dev_err(&pdev->dev, "could not get i2c bus node\n");
-- 
1.9.1

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[PATCH v3 5/8] ARM: dts: am335x-boneblack: Add blue-and-red-wiring -property to LCDC node

[Jyri Sarha]

Add blue-and-red-wiring -property to LCDC node. Also adds comments on
how to get support 24 bit RGB mode. After this patch am335x-boneblack
support RGB565, BGR888, and XBGR8888 color formats. See details in
Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt.

The BBB has straight color wiring from am335x to tda19988, however the
tda19988 can be configured to cross the blue and red wires. The
comments show how to do that with video-ports property of tda19988
node and how to tell LCDC that blue and red wires are crossed, with
blue-and-red-wiring LCDC node property. This changes supported color
formats from 16 bit RGB and 24 bit BGR to 16 bit BGR and 24 bit RGB.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 arch/arm/boot/dts/am335x-boneblack.dts | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index 528559b..8b87164 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -90,6 +90,14 @@
 
 &lcdc {
 	status = "okay";
+
+	/* If you want to get 24 bit RGB and 16 BGR mode instead of
+	 * current 16 bit RGB and 24 BGR modes, set the propety
+	 * below to "crossed" and uncomment the video-ports -property
+	 *in tda19988 node.
+	 */
+	blue-and-red-wiring = "straight";
+
 	port {
 		lcdc_0: endpoint@0 {
 			remote-endpoint = <&hdmi_0>;
@@ -106,6 +114,9 @@
 		pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
 		pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
 
+		/* Convert 24bit BGR to RGB, e.g. cross red and blue wiring */
+		/* video-ports = <0x234501>; */
+
 		#sound-dai-cells = <0>;
 		audio-ports = <	TDA998x_I2S	0x03>;
 
-- 
1.9.1

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[PATCH v3 6/8] ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node

[Jyri Sarha]

Add blue-and-red-wiring -property to lcdc node. The am335x-evm has
blue and red wires crossed to get 24-bit RGB (and 16-bit BGR)
support. After this patch am335x-evm supports BGR565, RGB888, and
XRGB8888 color formats. See details in
Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 arch/arm/boot/dts/am335x-evm.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 5d28712..c3cbce0 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -497,6 +497,8 @@
 
 &lcdc {
 	status = "okay";
+
+	blue-and-red-wiring = "crossed";
 };
 
 &elm {
-- 
1.9.1

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[PATCH v3 7/8] ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes

[Jyri Sarha]

Whitespace cleanup of lcdc related nodes. Do all indentation and
alignment with tabs instead of spaces.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 arch/arm/boot/dts/am335x-evmsk.dts | 40 +++++++++++++++++++-------------------
 1 file changed, 20 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 09308d6..23b94e7 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -170,29 +170,29 @@
 		pinctrl-1 = <&lcd_pins_sleep>;
 		status = "okay";
 		panel-info {
-			ac-bias           = <255>;
-			ac-bias-intrpt    = <0>;
-			dma-burst-sz      = <16>;
-			bpp               = <32>;
-			fdd               = <0x80>;
-			sync-edge         = <0>;
-			sync-ctrl         = <1>;
-			raster-order      = <0>;
-			fifo-th           = <0>;
+			ac-bias		= <255>;
+			ac-bias-intrpt	= <0>;
+			dma-burst-sz	= <16>;
+			bpp		= <32>;
+			fdd		= <0x80>;
+			sync-edge	= <0>;
+			sync-ctrl	= <1>;
+			raster-order	= <0>;
+			fifo-th		= <0>;
 		};
 		display-timings {
 			480x272 {
-				hactive         = <480>;
-				vactive         = <272>;
-				hback-porch     = <43>;
-				hfront-porch    = <8>;
-				hsync-len       = <4>;
-				vback-porch     = <12>;
-				vfront-porch    = <4>;
-				vsync-len       = <10>;
+				hactive		= <480>;
+				vactive		= <272>;
+				hback-porch	= <43>;
+				hfront-porch	= <8>;
+				hsync-len	= <4>;
+				vback-porch	= <12>;
+				vfront-porch	= <4>;
+				vsync-len	= <10>;
 				clock-frequency = <9000000>;
-				hsync-active    = <0>;
-				vsync-active    = <0>;
+				hsync-active	= <0>;
+				vsync-active	= <0>;
 			};
 		};
 	};
@@ -711,5 +711,5 @@
 };
 
 &lcdc {
-      status = "okay";
+	status = "okay";
 };
-- 
1.9.1

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[PATCH v3 8/8] ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node

[Jyri Sarha]

Add blue-and-red-wiring -property to lcdc node. The am335x-evmsk has
blue and red wires crossed to get 24-bit RGB (and 16-bit BGR)
support. After this patch am335x-evmsk supports BGR565, RGB888, and
XRGB8888 color formats. See details in
Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
 arch/arm/boot/dts/am335x-evmsk.dts | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 23b94e7..034e117 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -712,4 +712,6 @@
 
 &lcdc {
 	status = "okay";
+
+	blue-and-red-wiring = "crossed";
 };
-- 
1.9.1

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Re: [PATCH v3 0/8] drm/tilcdc: Address LCDC rev 2 color errata + other fixes

[Tony Lindgren]

* Jyri Sarha <jsarha-l0cyMroinI0@public.gmane.org> [160831 06:19]:
>   ARM: dts: am335x-boneblack: Add blue-and-red-wiring -property to LCDC
>     node
>   ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node
>   ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes
>   ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node

If some of these dts changes are OK for me to apply separately already,
please let me know.

Otherwise I'll tag this thread as read and assume you'll send the dts
changes separately when ready :)

Regards,

Tony
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Re: [PATCH v3 0/8] drm/tilcdc: Address LCDC rev 2 color errata + other fixes

[Jyri Sarha]

On 08/31/16 21:04, Tony Lindgren wrote:
> * Jyri Sarha <jsarha@ti.com> [160831 06:19]:
>>   ARM: dts: am335x-boneblack: Add blue-and-red-wiring -property to LCDC
>>     node
>>   ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node
>>   ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes
>>   ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node
> 
> If some of these dts changes are OK for me to apply separately already,
> please let me know.
> 
> Otherwise I'll tag this thread as read and assume you'll send the dts
> changes separately when ready :)
> 

According to my plan the drm side changes should go into 4.9.

The commit messages and the comments may look confusing without the
implementation, but otherwise there should be no harm in applying these
already. The new properties in dts simply wont have any effect. On the
other hand, not having the dts changes won't have any dramatic effect
either. The supported colour formats will just remain in the same
incorrect state as they have always been until the dts changes are
there. So what ever is more convenient for you.

Thanks,
Jyri
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Re: [PATCH v3 0/8] drm/tilcdc: Address LCDC rev 2 color errata + other fixes

[Tony Lindgren]

* Jyri Sarha <jsarha-l0cyMroinI0@public.gmane.org> [160831 11:49]:
> On 08/31/16 21:04, Tony Lindgren wrote:
> > * Jyri Sarha <jsarha-l0cyMroinI0@public.gmane.org> [160831 06:19]:
> >>   ARM: dts: am335x-boneblack: Add blue-and-red-wiring -property to LCDC
> >>     node
> >>   ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node
> >>   ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes
> >>   ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node
> > 
> > If some of these dts changes are OK for me to apply separately already,
> > please let me know.
> > 
> > Otherwise I'll tag this thread as read and assume you'll send the dts
> > changes separately when ready :)
> > 
> 
> According to my plan the drm side changes should go into 4.9.
> 
> The commit messages and the comments may look confusing without the
> implementation, but otherwise there should be no harm in applying these
> already. The new properties in dts simply wont have any effect. On the
> other hand, not having the dts changes won't have any dramatic effect
> either. The supported colour formats will just remain in the same
> incorrect state as they have always been until the dts changes are
> there. So what ever is more convenient for you.

OK well please ping me or resend just the dts changes once the driver
changes are queued. Probably safer to wait a bit in case things still
change.

Thanks,

Tony
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Re: [PATCH v3 2/8] drm/tilcdc: Write DMA base and ceiling address with single instruction

[Tomi Valkeinen]

[-- Attachment #1.1.1: Type: text/plain, Size: 1831 bytes --]

On 31/08/16 16:14, Jyri Sarha wrote:
> Write DMA base and ceiling address with a single instruction, if
> available. This should make it more unlikely that LCDC would fetch the
> DMA addresses in the middle of an update. Having bad combination of
> addresses in dma base and ceiling (e.g base > ceiling) can cause
> unpredictaple behavior in LCDC.
> 
> Signed-off-by: Jyri Sarha <jsarha@ti.com>
> ---
>  drivers/gpu/drm/tilcdc/tilcdc_crtc.c |  9 +++++++--
>  drivers/gpu/drm/tilcdc/tilcdc_regs.h | 14 ++++++++++++++
>  2 files changed, 21 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> index 6350f2a..41ec5b3 100644
> --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
> @@ -70,6 +70,7 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
>  	struct drm_gem_cma_object *gem;
>  	unsigned int depth, bpp;
>  	dma_addr_t start, end;
> +	u64 dma_base_and_ceiling;
>  
>  	drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
>  	gem = drm_fb_cma_get_gem_obj(fb, 0);
> @@ -80,8 +81,12 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
>  
>  	end = start + (crtc->mode.vdisplay * fb->pitches[0]);
>  
> -	tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, start);
> -	tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, end - 1);
> +	/* Write DMA base and ceiling address with a single insruction,
> +	 * if available. This should make it more unlikely that LCDC would
> +	 * fetch the DMA addresses in the middle of an update.
> +	 */

I think it would be good to have the register names mentioned in the
above comment. Otherwise I can imagine grepping for CEILING_ADDR, and
not finding it set anywhere in the driver...

 Tomi


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Re: [PATCH v3 2/8] drm/tilcdc: Write DMA base and ceiling address with single instruction

[Jyri Sarha]

On 09/01/16 10:13, Tomi Valkeinen wrote:
> On 31/08/16 16:14, Jyri Sarha wrote:
>> Write DMA base and ceiling address with a single instruction, if
>> available. This should make it more unlikely that LCDC would fetch the
>> DMA addresses in the middle of an update. Having bad combination of
>> addresses in dma base and ceiling (e.g base > ceiling) can cause
>> unpredictaple behavior in LCDC.
>>
>> Signed-off-by: Jyri Sarha <jsarha@ti.com>
>> ---
>>  drivers/gpu/drm/tilcdc/tilcdc_crtc.c |  9 +++++++--
>>  drivers/gpu/drm/tilcdc/tilcdc_regs.h | 14 ++++++++++++++
>>  2 files changed, 21 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
>> index 6350f2a..41ec5b3 100644
>> --- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
>> +++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
>> @@ -70,6 +70,7 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
>>  	struct drm_gem_cma_object *gem;
>>  	unsigned int depth, bpp;
>>  	dma_addr_t start, end;
>> +	u64 dma_base_and_ceiling;
>>  
>>  	drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
>>  	gem = drm_fb_cma_get_gem_obj(fb, 0);
>> @@ -80,8 +81,12 @@ static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
>>  
>>  	end = start + (crtc->mode.vdisplay * fb->pitches[0]);
>>  
>> -	tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, start);
>> -	tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG, end - 1);
>> +	/* Write DMA base and ceiling address with a single insruction,
>> +	 * if available. This should make it more unlikely that LCDC would
>> +	 * fetch the DMA addresses in the middle of an update.
>> +	 */
> 
> I think it would be good to have the register names mentioned in the
> above comment. Otherwise I can imagine grepping for CEILING_ADDR, and
> not finding it set anywhere in the driver...
> 

Ok, I'll do one more quick round for this patch. I also move the comment
before 64-bit assignment in tilcdc_write64() after the __iowmb();.

BR,
Jyri


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Re: [PATCH v3 3/8] drm/tilcdc: Add blue-and-red-crossed devicetree property

[Tomi Valkeinen]

[-- Attachment #1.1.1: Type: text/plain, Size: 2220 bytes --]



On 31/08/16 16:14, Jyri Sarha wrote:
> Add "blue-and-red-wiring"-device tree property and update devicetree
> binding document. The red and blue components are reversed between 24
> and 16 bit modes on am335x LCDC output pins. To get 24 RGB format the
> red and blue wires has to be crossed and this in turn causes 16 colors
> output to be in BGR format. With straight wiring the 16 color is RGB
> and 24 bit is BGR. The new property describes whether the red and blue
> wires are crossed or not. If the property is not present or its value
> is not recognized the legacy mode is assumed. The legacy configuration
> supports RGB565, RGB888 and XRGB8888 formats. However, depending on
> wiring, the red and blue colors are swapped in either 16 or 24-bit
> color modes.
> 
> For more details see section 3.1.1 in AM335x Silicon Errata:
> http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360
> 
> Signed-off-by: Jyri Sarha <jsarha@ti.com>
> ---
>  .../devicetree/bindings/display/tilcdc/tilcdc.txt  | 22 ++++++++++++
>  drivers/gpu/drm/tilcdc/tilcdc_drv.c                | 42 ++++++++++++++++++++++
>  drivers/gpu/drm/tilcdc/tilcdc_drv.h                |  4 +++
>  drivers/gpu/drm/tilcdc/tilcdc_plane.c              |  9 ++---
>  4 files changed, 71 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
> index 6efa4c5..5b7b5f8 100644
> --- a/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
> +++ b/Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt
> @@ -17,6 +17,18 @@ Optional properties:
>     the lcd controller.
>   - max-pixelclock: The maximum pixel clock that can be supported
>     by the lcd controller in KHz.
> + - blue-and-red-wiring: Recognized values "default", "straight" or
> +   "crossed". This property deals with the LCDC revision 2 (found on
> +   AM335x) color errata [1].
> +     - "default" and "straight" indicates normal wiring that supports

I didn't mean to add two values for this =). Just use one, there's no
benefit in supporting multiple values meaning the same thing.

 Tomi


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Re: [PATCH v3 0/8] drm/tilcdc: Address LCDC rev 2 color errata + other fixes

[Tomi Valkeinen]

[-- Attachment #1.1.1: Type: text/plain, Size: 1866 bytes --]

On 31/08/16 16:14, Jyri Sarha wrote:
> Changes since v2:
> - Fiddle with color wiring propety once more, now it follows this Tomi's
>   comment:
>   - No property set: driver advertises RG16 and RG24. This is
>     wrong, but that's what the current status is, right?
>   - Property set to "default" or "straight" or whatever: driver
>     says RG16 and BG24
>   - Property set to "crossed": driver says BG16 and RG24
> - Add v2 version of "drm/tilcdc: Write DMA base and ceiling address with..."
>   - The first version was sent individually, this second version has
>     __iowmb(); and __cpu_to_le64(); added to tilcdc_write64()
> 
> Changes since v1:
> - Change the blue-and-red-wiring property to boolean blue-and-red-crossed
>   - This breaks to little backward compatibility the earlier series had, but
>     makes the binding more straight forward
>   - This changes requires changes to am335x-evm and am335x-evmsk dts-files
>   - The old beaglebone-black dts files remain compatible, but the patch
>     suggests in commenst on how to support 24-bit RGB mode with BBB
> 
> The first patch ("drm/tilcdc: Remove drm_helper_disable_unused_functions()
> call") is completely independent fix.
> 
> The red and blue components are reversed between 24 and 16 bit modes
> on am335x LCDC output pins. To get 24 RGB format the wires red and
> blue wires has to be crossed and this in turn causes 16 colors output
> to be in BGR format. With straight wiring the 16 color is RGB and 24
> bit is BGR. These patches try to deal with the issue in reasonable
> manner.
> 
> For more details see section 3.1.1 in AM335x Silicon Errata:
> http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprz360

Aside the few minor comments I had, for the series:

Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>

 Tomi


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