[PATCH 0/6] LoongArch: Add built-in dtb support

[PATCH 0/6] LoongArch: Add built-in dtb support

[Binbin Zhou]

Hi all:

This patchset introduces LoongArch's built-in dtb support.

As we know, the Loongson-2K family supports DT. Inevitably, some systems
do not provide a useful device tree to the kernel at boot time. Chasing
around bootloaders for these systems is a headache, so we just keep a
device tree table in the kernel, keyed by the dts filename, that
contains the relevant DTBs.

Thanks.

Binbin Zhou (6):
  dt-bindings: loongarch: Add CPU bindings for LoongArch
  dt-bindings: loongarch: Add Loongson SoC boards compatibles
  LoongArch: Allow device trees to be built into the kernel
  LoongArch: DeviceTree for Loongson-2K0500
  LoongArch: DeviceTree for Loongson-2K1000
  LoongArch: DeviceTree for Loongson-2K2000

 .../devicetree/bindings/loongarch/boards.yaml |  31 +
 .../devicetree/bindings/loongarch/cpus.yaml   |  65 ++
 arch/loongarch/Kconfig                        |  16 +
 arch/loongarch/Makefile                       |  10 +-
 arch/loongarch/boot/dts/Makefile              |   7 +-
 arch/loongarch/boot/dts/loongson_2k0500.dts   | 311 ++++++++++
 arch/loongarch/boot/dts/loongson_2k1000.dts   | 565 ++++++++++++++++++
 arch/loongarch/boot/dts/loongson_2k2000.dts   | 417 +++++++++++++
 arch/loongarch/kernel/setup.c                 |   9 +-
 9 files changed, 1425 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/loongarch/boards.yaml
 create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
 create mode 100644 arch/loongarch/boot/dts/loongson_2k0500.dts
 create mode 100644 arch/loongarch/boot/dts/loongson_2k1000.dts
 create mode 100644 arch/loongarch/boot/dts/loongson_2k2000.dts

-- 
2.39.3

[PATCH 1/6] dt-bindings: loongarch: Add CPU bindings for LoongArch

[Binbin Zhou]

Add the available CPUs in LoongArch binding with DT schema format using
json-schema.

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
 .../devicetree/bindings/loongarch/cpus.yaml   | 65 +++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml

diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
new file mode 100644
index 000000000000..c3e2dba42c81
--- /dev/null
+++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LoongArch CPUs
+
+maintainers:
+  - Binbin Zhou <zhoubinbin@loongson.cn>
+
+description:
+  The device tree allows to describe the layout of CPUs in a system through
+  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
+  defining properties for every CPU.
+
+properties:
+  compatible:
+    enum:
+      - loongson,la264
+      - loongson,la364
+
+  reg:
+    maxItems: 1
+
+  device_type: true
+
+  clock-frequency:
+    description: The frequency of cpu in Hz.
+
+  model:
+    $ref: /schemas/types.yaml#/definitions/string
+    description: User-visible cpu name in /proc/cpuinfo.
+
+required:
+  - compatible
+  - reg
+  - clock-frequency
+
+additionalProperties: false
+
+examples:
+  - |
+    cpus {
+        #size-cells = <0>;
+        #address-cells = <1>;
+
+        model = "Loongson-2K1000";
+
+        cpu@0 {
+            compatible = "loongson,la264";
+            device_type = "cpu";
+            reg = <0>;
+            clock-frequency = <1000000000>;
+        };
+
+        cpu@1 {
+            compatible = "loongson,la264";
+            device_type = "cpu";
+            reg = <1>;
+            clock-frequency = <1000000000>;
+        };
+    };
+
+...
-- 
2.39.3

[PATCH 2/6] dt-bindings: loongarch: Add Loongson SoC boards compatibles

[Binbin Zhou]

Add Loongson SoC boards binding with DT schema format using json-schema

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
 .../devicetree/bindings/loongarch/boards.yaml | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/loongarch/boards.yaml

diff --git a/Documentation/devicetree/bindings/loongarch/boards.yaml b/Documentation/devicetree/bindings/loongarch/boards.yaml
new file mode 100644
index 000000000000..3ef87b732668
--- /dev/null
+++ b/Documentation/devicetree/bindings/loongarch/boards.yaml
@@ -0,0 +1,31 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/loongarch/boards.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson SoC-based boards
+
+maintainers:
+  - Binbin Zhou <zhoubinbin@loongson.cn>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Loongson-2K0500 processor based boards
+        items:
+          - const: loongson,ls2k0500
+
+      - description: Loongson-2K1000 processor based boards
+        items:
+          - const: loongson,ls2k1000
+
+      - description: Loongson-2K2000 processor based boards
+        items:
+          - const: loongson,ls2k2000
+
+additionalProperties: true
+
+...
-- 
2.39.3

[PATCH 3/6] LoongArch: Allow device trees to be built into the kernel

[Binbin Zhou]

Some systems do not provide a useful device tree to the kernel at boot
time. Let's keep a device tree table in the kernel, keyed by the dts
filename, containing the relevant DTBs.

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
---
 arch/loongarch/Kconfig           | 16 ++++++++++++++++
 arch/loongarch/Makefile          | 10 ++++++++--
 arch/loongarch/boot/dts/Makefile |  3 +--
 arch/loongarch/kernel/setup.c    |  9 +++++++--
 4 files changed, 32 insertions(+), 6 deletions(-)

diff --git a/arch/loongarch/Kconfig b/arch/loongarch/Kconfig
index 79412304a01f..ea78922b2ca9 100644
--- a/arch/loongarch/Kconfig
+++ b/arch/loongarch/Kconfig
@@ -308,6 +308,22 @@ config 64KB_3LEVEL
 
 endchoice
 
+config BUILTIN_DTB
+	bool "Enable builtin dtb in kernel"
+	depends on OF
+	help
+	  Some systems do not provide a useful device tree to the kernel at boot
+	  time. Let's keep a device tree table in the kernel, keyed by the dts
+	  filename, containing the relevant DTBs.
+
+config BUILTIN_DTB_NAME
+	string "Source file for LoongArch builtin dtb"
+	depends on BUILTIN_DTB
+	help
+	  Base name (without suffix, relative to arch/loongarch/boot/dts/)
+	  for the DTS file that will be used to produce the DTB linked into the
+	  kernel.
+
 config CMDLINE
 	string "Built-in kernel command line"
 	help
diff --git a/arch/loongarch/Makefile b/arch/loongarch/Makefile
index a27e264bdaa5..c8c2dd7d14e5 100644
--- a/arch/loongarch/Makefile
+++ b/arch/loongarch/Makefile
@@ -5,7 +5,8 @@
 
 boot	:= arch/loongarch/boot
 
-KBUILD_DEFCONFIG := loongson3_defconfig
+KBUILD_DEFCONFIG		:= loongson3_defconfig
+KBUILD_DTBS			:= dtbs
 
 image-name-y			:= vmlinux
 image-name-$(CONFIG_EFI_ZBOOT)	:= vmlinuz
@@ -130,11 +131,14 @@ PHONY += vdso_install
 vdso_install:
 	$(Q)$(MAKE) $(build)=arch/loongarch/vdso $@
 
-all:	$(notdir $(KBUILD_IMAGE))
+all:	$(notdir $(KBUILD_IMAGE)) $(KBUILD_DTBS)
 
 vmlinux.elf vmlinux.efi vmlinuz.efi: vmlinux
 	$(Q)$(MAKE) $(build)=$(boot) $(bootvars-y) $(boot)/$@
 
+# device-trees
+core-y += arch/loongarch/boot/dts/
+
 install:
 	$(Q)install -D -m 755 $(KBUILD_IMAGE) $(INSTALL_PATH)/$(image-name-y)-$(KERNELRELEASE)
 	$(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE)
@@ -142,5 +146,7 @@ install:
 
 define archhelp
 	echo '  install              - install kernel into $(INSTALL_PATH)'
+	echo '  dtbs                 - Device-tree blobs for enabled boards'
+	echo '  dtbs_install         - Install dtbs to $(INSTALL_DTBS_PATH)'
 	echo
 endef
diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index 5f1f55e911ad..1e24cdb5180a 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-only
-dtstree	:= $(srctree)/$(src)
 
-dtb-y := $(patsubst $(dtstree)/%.dts,%.dtb, $(wildcard $(dtstree)/*.dts))
+obj-$(CONFIG_BUILTIN_DTB)	+= $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
diff --git a/arch/loongarch/kernel/setup.c b/arch/loongarch/kernel/setup.c
index 4444b13418f0..1c5df6254248 100644
--- a/arch/loongarch/kernel/setup.c
+++ b/arch/loongarch/kernel/setup.c
@@ -296,8 +296,13 @@ static void __init fdt_setup(void)
 	if (acpi_os_get_root_pointer())
 		return;
 
-	/* Look for a device tree configuration table entry */
-	fdt_pointer = efi_fdt_pointer();
+	/* We prefer to try to use built-in dtb, checking its legality first. */
+	if (!fdt_check_header(__dtb_start))
+		fdt_pointer = __dtb_start;
+	else
+		/* Fallback to efi dtb, when built-in dtb is not available. */
+		fdt_pointer = efi_fdt_pointer();
+
 	if (!fdt_pointer || fdt_check_header(fdt_pointer))
 		return;
 
-- 
2.39.3

[PATCH 4/6] LoongArch: DeviceTree for Loongson-2K0500

[Binbin Zhou]

Add DeviceTree file for Loongson-2K0500 processor, which integrates one
64-bit dual emission superscalar LA264 processor core.

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
 arch/loongarch/boot/dts/Makefile            |   2 +
 arch/loongarch/boot/dts/loongson_2k0500.dts | 311 ++++++++++++++++++++
 2 files changed, 313 insertions(+)
 create mode 100644 arch/loongarch/boot/dts/loongson_2k0500.dts

diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index 1e24cdb5180a..0e5ed373b1b4 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
+dtb-$(CONFIG_MACH_LOONGSON64)	= loongson_2k0500.dtb
+
 obj-$(CONFIG_BUILTIN_DTB)	+= $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
diff --git a/arch/loongarch/boot/dts/loongson_2k0500.dts b/arch/loongarch/boot/dts/loongson_2k0500.dts
new file mode 100644
index 000000000000..4f58f7b06445
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson_2k0500.dts
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "LS2K0500 Reference Board";
+	compatible = "loongson,ls2k0500";
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		serial0 = &cpu_uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs = "earlycon";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		model = "Loongson-2K0500";
+
+		cpu0: cpu@0 {
+			compatible = "loongson,la264";
+			device_type = "cpu";
+			reg = <0x0>;
+			clock-frequency = <500000000>;	/* 500MHz */
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+			};
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */
+		      <0x00000000 0x90000000 0x00000000 0x60000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x00000000 0x02000000>;
+			linux,cma-default;
+		};
+	};
+
+	ref_100m: clock-ref-100m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "ref_100m";
+	};
+
+	cpuintc: interrupt-controller {
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		compatible = "loongson,cpu-interrupt-controller";
+	};
+
+	liointc0: interrupt-controller@1fe11400 {
+		compatible = "loongson,liointc-2.0";
+		reg = <0 0x1fe11400 0 0x40>,
+		      <0 0x1fe11040 0 0x8>;
+		reg-names = "main", "isr0";
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <2>;
+		interrupt-names = "int0";
+		loongson,parent_int_map = <0xffffffff>, /* int0 */
+					  <0x00000000>, /* int1 */
+					  <0x00000000>, /* int2 */
+					  <0x00000000>; /* int3 */
+	};
+
+	liointc1: interrupt-controller@1fe11440 {
+		compatible = "loongson,liointc-2.0";
+		reg = <0 0x1fe11440 0 0x40>,
+		      <0 0x1fe11048 0 0x8>;
+		reg-names = "main", "isr0";
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <4>;
+		interrupt-names = "int2";
+
+		loongson,parent_int_map = <0x00000000>, /* int0 */
+					  <0x00000000>, /* int1 */
+					  <0xffffffff>, /* int2 */
+					  <0x00000000>; /* int3 */
+	};
+
+	eiointc: interrupt-controller@1fe11600 {
+		compatible = "loongson,ls2k0500-eiointc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <3>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ranges = <0 0x10000000 0 0x10000000 0 0x10000000>,
+			 <0 0x2000000  0 0x2000000  0 0x2000000>,
+			 <0 0x20000000 0 0x20000000 0 0x10000000>,
+			 <0 0x40000000 0 0x40000000 0 0x40000000>,
+			 <0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
+
+		reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pmc>;
+			offset = <0x30>;
+			mask = <0x1>;
+		};
+
+		poweroff {
+			compatible = "syscon-poweroff";
+			regmap = <&pmc>;
+			offset = <0x14>;
+			mask = <0x3c00>;
+			value = <0x3c00>;
+		};
+
+		gmac0: ethernet@1f020000 {
+			compatible = "snps,dwmac-3.70a";
+			reg = <0 0x1f020000 0 0x10000>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			mac-address = [ 64 48 48 48 48 60 ];/* [>mac 64:48:48:48:48:60 <]*/
+			phy-mode = "rgmii";
+			bus_id = <0x0>;
+		};
+
+		gmac1: ethernet@1f030000 {
+			compatible = "snps,dwmac-3.70a";
+			reg = <0 0x1f030000 0 0x10000>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			mac-address = [ 64 48 48 48 48 61 ];/* [>mac 64:48:48:48:48:61 <]*/
+			phy-mode = "rgmii";
+			bus_id = <0x1>;
+		};
+
+		sata@1f040000 {
+			compatible = "snps,spear-ahci";
+			reg = <0 0x1f040000 0 0x10000>;
+			interrupt-parent = <&eiointc>;
+			interrupts = <75>;
+		};
+
+		ehci@1f050000 {
+			compatible = "generic-ehci";
+			reg = <0 0x1f050000 0 0x8000>;
+			interrupt-parent = <&eiointc>;
+			interrupts = <71>;
+		};
+
+		ohci@1f058000 {
+			compatible = "generic-ohci";
+			reg = <0 0x1f058000 0 0x8000>;
+			interrupt-parent = <&eiointc>;
+			interrupts = <72>;
+		};
+
+		clk: clock-controller@1fe10400 {
+			compatible = "loongson,ls2k-clk";
+			reg = <0 0x1fe00400 0 0x30>;
+			#clock-cells = <1>;
+			clocks = <&ref_100m>;
+			clock-names = "ref_100m";
+			status = "disabled";
+		};
+
+		cpu_uart0: serial@1ff40800 {
+			compatible = "ns16550a";
+			reg = <0 0x1ff40800 0 0x10>;
+			clock-frequency = <100000000>;
+			interrupt-parent = <&eiointc>;
+			interrupts = <2>;
+			no-loopback-test;
+		};
+
+		i2c@1ff48000 {
+			compatible = "loongson,ls2k-i2c";
+			reg = <0 0x1ff48000 0 0x0800>;
+			interrupt-parent = <&eiointc>;
+			interrupts = <14>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			eeprom@57 {
+				compatible = "atmel,24c16";
+				reg = <0x57>;
+				pagesize = <16>;
+			};
+		};
+
+		i2c@1ff48800 {
+			compatible = "loongson,ls2k-i2c";
+			reg = <0 0x1ff48800 0 0x0800>;
+			interrupt-parent = <&eiointc>;
+			interrupts = <15>;
+			status = "disabled";
+		};
+
+		i2c@1ff49000 {
+			compatible = "loongson,ls2k-i2c";
+			reg = <0 0x1ff49000 0 0x0800>;
+			interrupt-parent = <&eiointc>;
+			interrupts = <16>;
+			status = "disabled";
+		};
+
+		i2c@1ff49800 {
+			compatible = "loongson,ls2k-i2c";
+			reg = <0 0x1ff49800 0 0x0800>;
+			interrupt-parent = <&eiointc>;
+			interrupts = <17>;
+			status = "disabled";
+		};
+
+		pixi2c@1ff4a000 {
+			compatible = "loongson,ls2k-i2c";
+			reg = <0 0x1ff4a000 0 0x0800>;
+			interrupt-parent = <&eiointc>;
+			interrupts = <18>;
+			status = "disabled";
+		};
+
+		pixi2c@1ff4a800 {
+			compatible = "loongson,ls2k-i2c";
+			reg = <0 0x1ff4a800 0 0x0800>;
+			interrupt-parent = <&eiointc>;
+			interrupts = <19>;
+			status = "disabled";
+		};
+
+		pmc: acpi@1ff6c000 {
+			compatible = "syscon";
+			reg = <0x0 0x1ff6c000 0x0 0x58>;
+			interrupt-parent = <&eiointc>;
+			interrupts = <56>;
+			suspend-address = <0x1c000500>;
+		};
+
+		pcie@16800000 {
+			compatible = "loongson,ls2k-pci";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			reg = <0 0x1a000000 0 0x02000000>,
+			      <0xfe 0x00000000 0 0x20000000>;
+
+			ranges = <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>,
+				 <0x01000000 0 0x00004000 0 0x16404000 0x0 0x4000>;
+
+			pci_bridge@0,0 {
+				compatible = "pci0014,1a05.1",
+					     "pci0014,1a05",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x0000 0x0 0x0 0x0 0x0>;
+				interrupts = <81>;
+				interrupt-parent = <&eiointc>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &eiointc 81>;
+			};
+
+			pci_bridge@1,0 {
+				compatible = "pci0014,1a05.1",
+					     "pci0014,1a05",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x0800 0x0 0x0 0x0 0x0>;
+				interrupts = <82>;
+				interrupt-parent = <&eiointc>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &eiointc 82>;
+			};
+		};
+	};
+};
-- 
2.39.3

[PATCH 5/6] LoongArch: DeviceTree for Loongson-2K1000

[Binbin Zhou]

Add DeviceTree file for Loongson-2K1000 processor, which integrates two
64-bit dual emission superscalar LA264 processor cores.

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
 arch/loongarch/boot/dts/Makefile            |   3 +-
 arch/loongarch/boot/dts/loongson_2k1000.dts | 565 ++++++++++++++++++++
 2 files changed, 567 insertions(+), 1 deletion(-)
 create mode 100644 arch/loongarch/boot/dts/loongson_2k1000.dts

diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index 0e5ed373b1b4..c0464bb8e430 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-dtb-$(CONFIG_MACH_LOONGSON64)	= loongson_2k0500.dtb
+dtb-$(CONFIG_MACH_LOONGSON64)	= loongson_2k0500.dtb \
+				  loongson_2k1000.dtb
 
 obj-$(CONFIG_BUILTIN_DTB)	+= $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
diff --git a/arch/loongarch/boot/dts/loongson_2k1000.dts b/arch/loongarch/boot/dts/loongson_2k1000.dts
new file mode 100644
index 000000000000..9fd9d400d97f
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson_2k1000.dts
@@ -0,0 +1,565 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/loongson,ls2k-clk.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "LS2K1000 Reference Board";
+	compatible = "loongson,ls2k1000";
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &cpu_uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs = "earlycon";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		model = "Loongson-2K1000";
+
+		cpu0: cpu@0 {
+			compatible = "loongson,la264";
+			device_type = "cpu";
+			reg= <0x0>;
+			clock-frequency = <1000000000>;	/*1000 MHz*/
+		};
+
+		cpu1: cpu@1 {
+			compatible = "loongson,la264";
+			device_type = "cpu";
+			reg = <0x1>;
+			clock-frequency = <1000000000>;	/*1000 MHz*/
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00200000 0x00000000 0x06e00000>,
+		      <0x00000000 0x08000000 0x00000000 0x07000000>,
+		      <0x00000000 0x90000000 0x00000001 0xe0000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x00000000 0x02000000>;
+			linux,cma-default;
+		};
+	};
+
+	memalloc@0 {
+		compatible = "loongson,ls-memalloc";
+		reg = <0 0x90000000 0 0x20000000>;
+	};
+
+	ref_100m: clock-ref-100m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "ref_100m";
+	};
+
+	cpuintc: interrupt-controller {
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		compatible = "loongson,cpu-interrupt-controller";
+	};
+
+	liointc0: interrupt-controller@1fe11400 {
+		compatible = "loongson,liointc-2.0";
+		reg = <0 0x1fe01400 0 0x40>,
+		      <0 0x1fe01040 0 0x8>,
+		      <0 0x1fe01140 0 0x8>;
+		reg-names = "main", "isr0", "isr1";
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <2>;
+		interrupt-names = "int0";
+		loongson,parent_int_map = <0xffffffff>, /* int0 */
+					  <0x00000000>, /* int1 */
+					  <0x00000000>, /* int2 */
+					  <0x00000000>; /* int3 */
+	};
+
+	liointc1: interrupt-controller@1fe11440 {
+		compatible = "loongson,liointc-2.0";
+		reg = <0 0x1fe01440 0 0x40>,
+		      <0 0x1fe01048 0 0x8>,
+		      <0 0x1fe01148 0 0x8>;
+		reg-names = "main", "isr0", "isr1";
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <3>;
+		interrupt-names = "int1";
+		loongson,parent_int_map = <0x00000000>, /* int0 */
+					  <0xffffffff>, /* int1 */
+					  <0x00000000>, /* int2 */
+					  <0x00000000>; /* int3 */
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ranges = <0 0x10000000 0 0x10000000 0 0x10000000>,
+			 <0 0x2000000 0 0x2000000 0 0x2000000>,
+			 <0 0x20000000 0 0x20000000 0 0x10000000>,
+			 <0 0x40000000 0 0x40000000 0 0x40000000>,
+			 <0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
+
+		dma-coherent;
+
+		reboot {
+			compatible ="syscon-reboot";
+			regmap = <&pmc>;
+			offset = <0x30>;
+			mask = <0x1>;
+		};
+
+		poweroff {
+			compatible ="syscon-poweroff";
+			regmap = <&pmc>;
+			offset = <0x14>;
+			mask = <0x3c00>;
+			value = <0x3c00>;
+		};
+
+		chipid@1fe00000 {
+			compatible = "loongson,ls2k-chipid";
+			reg = <0 0x1fe00000 0 0x3ffc>;
+			little-endian;
+		};
+
+		pctrl: pinctrl@1fe00420 {
+			compatible = "loongson,ls2k-pinctrl";
+			reg = <0 0x1fe00420 0 0x18>;
+
+			sdio_pins_default: sdio-pins {
+				sdio-pinmux {
+					groups = "sdio";
+					function = "sdio";
+				};
+				sdio-det-pinmux {
+					groups = "pwm2";
+					function = "gpio";
+				};
+			};
+
+			pwm1_pins_default: pwm1-pins {
+				pinmux {
+					groups = "pwm1";
+					function = "pwm1";
+				};
+			};
+
+			pwm0_pins_default: pwm0-pins {
+				pinmux {
+					groups = "pwm0";
+					function = "pwm0";
+				};
+			};
+
+			i2c1_pins_default: i2c1-pins {
+				pinmux {
+					groups = "i2c1";
+					function = "i2c1";
+				};
+			};
+
+			i2c0_pins_default: i2c0-pins {
+				pinmux {
+					groups = "i2c0";
+					function = "i2c0";
+				};
+			};
+
+			nand_pins_default: nand-pins {
+				pinmux {
+					groups = "nand";
+					function = "nand";
+				};
+			};
+
+			hda_pins_default: hda-pins {
+				grp0-pinmux {
+					groups = "hda";
+					function = "hda";
+				};
+				grp1-pinmux {
+					groups = "i2s";
+					function = "gpio";
+				};
+			};
+		};
+
+		clk: clock-controller@1fe00480 {
+			compatible = "loongson,ls2k-clk";
+			reg = <0 0x1fe00480 0 0x58>;
+			#clock-cells = <1>;
+			clocks = <&ref_100m>;
+			clock-names = "ref_100m";
+		};
+
+		gpio0: gpio@1fe00500 {
+			compatible = "loongson,ls2k-gpio", "syscon";
+			reg = <0 0x1fe00500 0 0x38>;
+			ngpios = <64>;
+			#gpio-cells = <2>;
+			gpio-controller;
+			interrupt-parent = <&liointc1>;
+			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>,
+				     <29 IRQ_TYPE_LEVEL_HIGH>,
+				     <30 IRQ_TYPE_LEVEL_HIGH>,
+				     <30 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <26 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <>,
+				     <>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>,
+				     <27 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		cpu_uart0: serial@1fe20000 {
+			compatible = "ns16550a";
+			reg = <0 0x1fe20000 0 0x10>;
+			clock-frequency = <125000000>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+			no-loopback-test;
+		};
+
+		i2c2: i2c@1fe21000 {
+			compatible = "loongson,ls2k-i2c";
+			reg = <0 0x1fe21000 0 0x8>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-0 = <&i2c0_pins_default>;
+			pinctrl-names = "default";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			eeprom@57{
+				compatible = "atmel,24c16";
+				reg = <0x57>;
+				pagesize = <16>;
+			};
+		};
+
+		i2c3: i2c@1fe21800 {
+			compatible = "loongson,ls2k-i2c";
+			reg = <0 0x1fe21800 0 0x8>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-0 = <&i2c1_pins_default>;
+			pinctrl-names = "default";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			codec@1a {
+				compatible = "codec_uda1342";
+				reg = <0x1a>;
+			};
+		};
+
+		pmc: acpi@1fe27000 {
+			compatible = "syscon";
+			reg = <0x0 0x1fe27000 0x0 0x58>;
+			interrupt-parent = <&liointc1>;
+			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+			suspend-address = <0x1c000500>;
+		};
+
+		pcie@60000000 {
+			compatible = "loongson,ls2k-pci";
+			device_type = "pci";
+			#size-cells = <2>;
+			#address-cells = <3>;
+
+			reg = <0 0x1a000000 0 0x02000000>,
+			      <0xfe 0x00000000 0 0x20000000>;
+			ranges = <0x01000000 0x0 0x00008000 0x0 0x18008000 0x0 0x00008000>,
+				 <0x02000000 0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>; /* mem */
+
+			ethernet@3,0 {
+				compatible = "pci0014,7a03.0",
+					     "pci0014,7a03",
+					     "pciclass,020000",
+					     "pciclass,0200",
+					     "loongson, pci-gmac";
+
+				reg = <0x1800 0x0 0x0 0x0 0x0>;
+				interrupt-parent = <&liointc0>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
+					     <13 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "macirq", "eth_lpi";
+
+				phy-mode = "rgmii";
+				phy-handle = <&phy0>;
+				mdio {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "snps,dwmac-mdio";
+					phy0: ethernet-phy@0 {
+						reg = <0>;
+					};
+				};
+			};
+
+			ethernet@3,1 {
+				compatible = "pci0014,7a03.0",
+					     "pci0014,7a03",
+					     "pciclass,020000",
+					     "pciclass,0200",
+					     "loongson, pci-gmac";
+
+				reg = <0x1900 0x0 0x0 0x0 0x0>;
+				interrupt-parent = <&liointc0>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
+					     <15 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "macirq", "eth_lpi";
+
+				phy-mode = "rgmii";
+				phy-handle = <&phy1>;
+				mdio {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "snps,dwmac-mdio";
+					phy1: ethernet-phy@1 {
+						reg = <16>;
+					};
+				};
+			};
+
+			ehci@4,1 {
+				compatible = "pci0014,7a14.0",
+					     "pci0014,7a14",
+					     "pciclass,0c0320",
+					     "pciclass,0c03";
+
+				reg = <0x2100 0x0 0x0 0x0 0x0>;
+				interrupt-parent = <&liointc1>;
+				interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			ohci@4,2 {
+				compatible = "pci0014,7a24.0",
+					     "pci0014,7a24",
+					     "pciclass,0c0310",
+					     "pciclass,0c03";
+
+				reg = <0x2200 0x0 0x0 0x0 0x0>;
+				interrupt-parent = <&liointc1>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			dc@6,0 {
+				compatible = "pci0014,7a06.0",
+					     "pci0014,7a06",
+					     "pciclass,030000",
+					     "pciclass,0300";
+
+				reg = <0x3000 0x0 0x0 0x0 0x0>;
+				interrupt-parent = <&liointc0>;
+				interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			hda@7,0 {
+				compatible = "pci0014,7a07.0",
+					     "pci0014,7a07",
+					     "pciclass,040300",
+					     "pciclass,0403";
+
+				reg = <0x3800 0x0 0x0 0x0 0x0>;
+				interrupt-parent = <&liointc0>;
+				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			sata@8,0 {
+				compatible = "pci0014,7a08.0",
+					     "pci0014,7a08",
+					     "pciclass,010601",
+					     "pciclass,0106";
+
+				reg = <0x4000 0x0 0x0 0x0 0x0>;
+				interrupt-parent = <&liointc0>;
+				interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			pci_bridge@9,0 {
+				compatible = "pci0014,7a19.1",
+					     "pci0014,7a19",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x4800 0x0 0x0 0x0 0x0>;
+				interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&liointc1>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			pci_bridge@a,0 {
+				compatible = "pci0014,7a09.1",
+					     "pci0014,7a09",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x5000 0x0 0x0 0x0 0x0>;
+				interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&liointc1>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			pci_bridge@b,0 {
+				compatible = "pci0014,7a09.1",
+					     "pci0014,7a09",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x5800 0x0 0x0 0x0 0x0>;
+				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&liointc1>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			pci_bridge@c,0 {
+				compatible = "pci0014,7a09.1",
+					     "pci0014,7a09",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x6000 0x0 0x0 0x0 0x0>;
+				interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&liointc1>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			pci_bridge@d,0 {
+				compatible = "pci0014,7a19.1",
+					     "pci0014,7a19",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x6800 0x0 0x0 0x0 0x0>;
+				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&liointc1>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			pci_bridge@e,0 {
+				compatible = "pci0014,7a09.1",
+					     "pci0014,7a09",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x7000 0x0 0x0 0x0 0x0>;
+				interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&liointc1>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+		};
+	};
+};
-- 
2.39.3

[PATCH 6/6] LoongArch: DeviceTree for Loongson-2K2000

[Binbin Zhou]

Add DeviceTree file for Loongson-2K2000 processor, which integrates two
64-bit triple emission superscalar LA364 processor cores.

Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
 arch/loongarch/boot/dts/Makefile            |   3 +-
 arch/loongarch/boot/dts/loongson_2k2000.dts | 417 ++++++++++++++++++++
 2 files changed, 419 insertions(+), 1 deletion(-)
 create mode 100644 arch/loongarch/boot/dts/loongson_2k2000.dts

diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index c0464bb8e430..71af680bd30d 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
 dtb-$(CONFIG_MACH_LOONGSON64)	= loongson_2k0500.dtb \
-				  loongson_2k1000.dtb
+				  loongson_2k1000.dtb \
+				  loongson_2k2000.dtb
 
 obj-$(CONFIG_BUILTIN_DTB)	+= $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
diff --git a/arch/loongarch/boot/dts/loongson_2k2000.dts b/arch/loongarch/boot/dts/loongson_2k2000.dts
new file mode 100644
index 000000000000..19ed16677e6c
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson_2k2000.dts
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	model = "LS2K2000 Reference Board";
+	compatible = "loongson,ls2k2000";
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+		bootargs = "earlycon";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		model = "Loongson-2K2000";
+
+		cpu0: cpu@1 {
+			compatible = "loongson,la364";
+			device_type = "cpu";
+			reg = <0x0>;
+			clock-frequency = <1200000000>;	/* 1500 MHz */
+		};
+
+		cpu1: cpu@2 {
+			compatible = "loongson,la364";
+			device_type = "cpu";
+			reg = <0x1>;
+			clock-frequency = <1200000000>;	/* 1500 MHz */
+		};
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+		};
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */
+		      <0x00000000 0x90000000 0x00000000 0x70000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x00000000 0x02000000>;
+			linux,cma-default;
+		};
+	};
+
+	cpuintc: interrupt-controller {
+		#interrupt-cells = <1>;
+		interrupt-controller;
+		compatible = "loongson,cpu-interrupt-controller";
+	};
+
+	liointc: interrupt-controller@1fe01400 {
+		compatible = "loongson,liointc-2.0";
+		reg = <0 0x1fe01400 0 0x40>,
+		      <0 0x1fe01440 0 0x8>,
+		      <0 0x1fe01448 0 0x8>;
+		reg-names = "main", "isr0", "isr1";
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <2>;
+		interrupt-names = "int0";
+		loongson,parent_int_map = <0xffffffff>, /* int0 */
+					  <0x00000000>, /* int1 */
+					  <0x00000000>, /* int2 */
+					  <0x00000000>; /* int3 */
+	};
+
+	eiointc: interrupt-controller@1fe01600 {
+		compatible = "loongson,ls2k2000-eiointc";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		interrupt-parent = <&cpuintc>;
+		interrupts = <3>;
+	};
+
+	pic: interrupt-controller@10000040 {
+		compatible = "loongson,pch-pic-1.0";
+		reg = <0x0 0x10000000 0x0 0x400>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+		loongson,pic-base-vec = <0>;
+		interrupt-parent = <&eiointc>;
+	};
+
+	msi: interrupt-controller@1fe01140 {
+		compatible = "loongson,pch-msi-1.0";
+		reg = <0 0x1fe01140 0 0x8>;
+		interrupt-controller;
+		loongson,msi-base-vec = <64>;
+		loongson,msi-num-vecs = <192>;
+		interrupt-parent = <&eiointc>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		ranges = <0 0x10000000 0 0x10000000 0 0x10000000>,
+			 <0 0x2000000  0 0x2000000  0 0x2000000>,
+			 <0 0x40000000 0 0x40000000 0 0x40000000>,
+			 <0xfe 0x00000000 0xfe 0 0 0x40000000>;
+
+		pmc: acpi@100d0000 {
+			compatible = "syscon";
+			reg = <0x0 0x100d0000 0x0 0x58>;
+			interrupt-parent = <&pic>;
+			interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
+			suspend-address = <0x1c000500>;
+		};
+
+		reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pmc>;
+			offset = <0x30>;
+			mask = <0x1>;
+		};
+
+		poweroff {
+			compatible = "syscon-poweroff";
+			regmap = <&pmc>;
+			offset = <0x14>;
+			mask = <0x3c00>;
+			value = <0x3c00>;
+		};
+
+		uart0: serial@1fe001e0 {
+			compatible = "ns16550a";
+			reg = <0 0x1fe001e0 0 0x10>;
+			clock-frequency = <100000000>;
+			interrupt-parent = <&liointc>;
+			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+			no-loopback-test;
+		};
+
+		pcie@60000000 {
+			compatible = "loongson,ls2k-pci";
+			device_type = "pci";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			msi-parent = <&msi>;
+
+			reg = <0 0x1a000000 0 0x02000000>,
+			      <0xfe 0x00000000 0 0x20000000>;
+
+			ranges = <0x02000000 0 0x60000000 0 0x60000000 0 0x20000000>,
+				 <0x01000000 0 0x00008000 0 0x18400000 0x0 0x8000>;
+
+			ethernet@3,0 {
+				compatible = "pci0014,7a13.0",
+					     "pci0014,7a13",
+					     "pciclass,020000",
+					     "pciclass,0200",
+					     "loongson, pci-gmac";
+
+				reg = <0x1800 0x0 0x0 0x0 0x0>;
+				interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				status = "disabled";
+			};
+
+			ethernet@3,1 {
+				compatible = "pci0014,7a13.0",
+					     "pci0014,7a13",
+					     "pciclass,020000",
+					     "pciclass,0200",
+					     "loongson, pci-gmac";
+
+				reg = <0x1900 0x0 0x0 0x0 0x0>;
+				interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+			};
+
+			ethernet@3,2 {
+				compatible = "pci0014,7a13.0",
+					     "pci0014,7a13",
+					     "pciclass,020000",
+					     "pciclass,0200",
+					     "loongson, pci-gmac";
+
+				reg = <0x1a00 0x0 0x0 0x0 0x0>;
+				interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+			};
+
+			usb@4,0 {
+				compatible = "pci0014,7a44.0",
+					     "pci0014,7a44",
+					     "pciclass,0c0330",
+					     "pciclass,0c03";
+
+				reg = <0x2000 0x0 0x0 0x0 0x0>;
+				interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+			};
+
+			usb@19,0 {
+				compatible = "pci0014,7a34.0",
+					     "pci0014,7a34",
+					     "pciclass,0c0330",
+					     "pciclass,0c03";
+
+				reg = <0xc800 0x0 0x0 0x0 0x0>;
+				interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+			};
+
+			dc@6,1 {
+				compatible = "pci0014,7a16.0",
+					     "pci0014,7a16",
+					     "pciclass,030000",
+					     "pciclass,0300";
+
+				reg = <0x3100 0x0 0x0 0x0 0x0>;
+				interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				status = "disabled";
+			};
+
+			hda@7,0 {
+				compatible = "pci0014,7a07.0",
+					     "pci0014,7a07",
+					     "pciclass,040300",
+					     "pciclass,0403";
+
+				reg = <0x3800 0x0 0x0 0x0 0x0>;
+				interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				status = "disabled";
+			};
+
+			sata@8,0 {
+				compatible = "pci0014,7a18.0",
+					     "pci0014,7a18",
+					     "pciclass,010601",
+					     "pciclass,0106";
+
+				reg = <0x4000 0x0 0x0 0x0 0x0>;
+				interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+			};
+
+			pci_bridge@9,0 {
+				compatible = "pci0014,7a49.1",
+					     "pci0014,7a49",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x4800 0x0 0x0 0x0 0x0>;
+				interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &pic 322 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			pci_bridge@a,0 {
+				compatible = "pci0014,7a39.1",
+					     "pci0014,7a39",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x5000 0x0 0x0 0x0 0x0>;
+				interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			pci_bridge@b,0 {
+				compatible = "pci0014,7a39.1",
+					     "pci0014,7a39",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x5800 0x0 0x0 0x0 0x0>;
+				interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			pci_bridge@c,0 {
+				compatible = "pci0014,7a39.1",
+					     "pci0014,7a39",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x6000 0x0 0x0 0x0 0x0>;
+				interrupts = <35 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			pci_bridge@d,0 {
+				compatible = "pci0014,7a49.1",
+					     "pci0014,7a49",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x6800 0x0 0x0 0x0 0x0>;
+				interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			pci_bridge@e,0 {
+				compatible = "pci0014,7a49.1",
+					     "pci0014,7a49",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x7000 0x0 0x0 0x0 0x0>;
+				interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			pci_bridge@f,0 {
+				compatible = "pci0014,7a79.1",
+					     "pci0014,7a79",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x7800 0x0 0x0 0x0 0x0>;
+				interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			pci_bridge@10,0 {
+				compatible = "pci0014,7a39.1",
+					     "pci0014,7a39",
+					     "pciclass,060400",
+					     "pciclass,0604";
+
+				reg = <0x8000 0x0 0x0 0x0 0x0>;
+				interrupts = <30 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &pic 30 IRQ_TYPE_LEVEL_HIGH>;
+				external-facing;
+			};
+
+			rio@18,0 {
+				compatible = "pci0014,7a1d.0",
+					     "pci0014,7a1d",
+					     "pciclass,068000",
+					     "pciclass,0680";
+
+				reg = <0xc000 0x0 0x0 0x0 0x0>;
+				interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				status = "disabled";
+			};
+
+			rio@1b,0 {
+				compatible = "pci0014,7a1d.0",
+					     "pci0014,7a1d",
+					     "pciclass,068000",
+					     "pciclass,0680";
+
+				reg = <0xd800 0x0 0x0 0x0 0x0>;
+				interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-parent = <&pic>;
+				status = "disabled";
+			};
+		};
+	};
+};
-- 
2.39.3

Re: [PATCH 1/6] dt-bindings: loongarch: Add CPU bindings for LoongArch

[Conor Dooley]

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On Fri, Jun 16, 2023 at 02:10:38PM +0800, Binbin Zhou wrote:
> Add the available CPUs in LoongArch binding with DT schema format using
> json-schema.
> 
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
>  .../devicetree/bindings/loongarch/cpus.yaml   | 65 +++++++++++++++++++
>  1 file changed, 65 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
> 
> diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> new file mode 100644
> index 000000000000..c3e2dba42c81
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: LoongArch CPUs
> +
> +maintainers:
> +  - Binbin Zhou <zhoubinbin@loongson.cn>
> +
> +description:
> +  The device tree allows to describe the layout of CPUs in a system through
> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> +  defining properties for every CPU.
> +
> +properties:
> +  compatible:
> +    enum:
> +      - loongson,la264
> +      - loongson,la364
> +
> +  reg:
> +    maxItems: 1
> +
> +  device_type: true
> +
> +  clock-frequency:
> +    description: The frequency of cpu in Hz.

Why don't you just add a ref to the common cpu schema and use the
standard properties for communicating clock frequencies?
You then get the standard properties for l1 caches, power management,
frequency scaling etc as a side effect.

Cheers,
Conor.

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Re: [PATCH 2/6] dt-bindings: loongarch: Add Loongson SoC boards compatibles

[Conor Dooley]

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On Fri, Jun 16, 2023 at 02:10:39PM +0800, Binbin Zhou wrote:
> Add Loongson SoC boards binding with DT schema format using json-schema
> 
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
>  .../devicetree/bindings/loongarch/boards.yaml | 31 +++++++++++++++++++
>  1 file changed, 31 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/loongarch/boards.yaml
> 
> diff --git a/Documentation/devicetree/bindings/loongarch/boards.yaml b/Documentation/devicetree/bindings/loongarch/boards.yaml
> new file mode 100644
> index 000000000000..3ef87b732668
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/loongarch/boards.yaml
> @@ -0,0 +1,31 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/loongarch/boards.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Loongson SoC-based boards
> +
> +maintainers:
> +  - Binbin Zhou <zhoubinbin@loongson.cn>
> +
> +properties:
> +  $nodename:
> +    const: '/'
> +  compatible:
> +    oneOf:
> +      - description: Loongson-2K0500 processor based boards
> +        items:
> +          - const: loongson,ls2k0500
> +
> +      - description: Loongson-2K1000 processor based boards
> +        items:
> +          - const: loongson,ls2k1000
> +
> +      - description: Loongson-2K2000 processor based boards
> +        items:
> +          - const: loongson,ls2k2000

From what I do know of loongarch stuff, these are all compatibles
for SoCs, not boards. The usual model would be to do something like
items:
  - const: loongsoon,ls2k1000-dev-kit
  - const: loongsoon,ls2k1000

Where you have a compatible for the SoC and one for the board.

Cheers,
Conor.

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Re: [PATCH 1/6] dt-bindings: loongarch: Add CPU bindings for LoongArch

[Krzysztof Kozlowski]

On 16/06/2023 11:34, Conor Dooley wrote:
> On Fri, Jun 16, 2023 at 02:10:38PM +0800, Binbin Zhou wrote:
>> Add the available CPUs in LoongArch binding with DT schema format using
>> json-schema.
>>
>> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
>> ---
>>  .../devicetree/bindings/loongarch/cpus.yaml   | 65 +++++++++++++++++++
>>  1 file changed, 65 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
>> new file mode 100644
>> index 000000000000..c3e2dba42c81
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
>> @@ -0,0 +1,65 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: LoongArch CPUs
>> +
>> +maintainers:
>> +  - Binbin Zhou <zhoubinbin@loongson.cn>
>> +
>> +description:
>> +  The device tree allows to describe the layout of CPUs in a system through
>> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>> +  defining properties for every CPU.
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - loongson,la264
>> +      - loongson,la364
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  device_type: true
>> +
>> +  clock-frequency:
>> +    description: The frequency of cpu in Hz.
> 
> Why don't you just add a ref to the common cpu schema and use the
> standard properties for communicating clock frequencies?
> You then get the standard properties for l1 caches, power management,
> frequency scaling etc as a side effect.
> 

And operating-points-v2... unless all Loongson CPUs work with only one
frequency and do not allow dynamic scaling?


Best regards,
Krzysztof

Re: [PATCH 5/6] LoongArch: DeviceTree for Loongson-2K1000

[Conor Dooley]

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On Fri, Jun 16, 2023 at 02:11:31PM +0800, Binbin Zhou wrote:

> +	memalloc@0 {
> +		compatible = "loongson,ls-memalloc";
> +		reg = <0 0x90000000 0 0x20000000>;
> +	};

This is not documented.

> +		gpio0: gpio@1fe00500 {
> +			compatible = "loongson,ls2k-gpio", "syscon";

This isn't valid either, the binding doesn't allow syscon?

> +			ethernet@3,1 {
> +				compatible = "pci0014,7a03.0",
> +					     "pci0014,7a03",
> +					     "pciclass,020000",
> +					     "pciclass,0200",
> +					     "loongson, pci-gmac";

None of the compatibles from here on out are documented either.

Cheers,
Conor.

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Re: [PATCH 1/6] dt-bindings: loongarch: Add CPU bindings for LoongArch

[Krzysztof Kozlowski]

On 16/06/2023 08:10, Binbin Zhou wrote:
> Add the available CPUs in LoongArch binding with DT schema format using
> json-schema.
> 
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
>  .../devicetree/bindings/loongarch/cpus.yaml   | 65 +++++++++++++++++++
>  1 file changed, 65 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
> 
> diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> new file mode 100644
> index 000000000000..c3e2dba42c81
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> @@ -0,0 +1,65 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: LoongArch CPUs
> +
> +maintainers:
> +  - Binbin Zhou <zhoubinbin@loongson.cn>
> +
> +description:
> +  The device tree allows to describe the layout of CPUs in a system through
> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> +  defining properties for every CPU.

I understand you copied it from ARM, but I would prefer to have here
something meaningful. Bindings description does not explain what is DTS,
but explains what the hardware is.

> +
> +properties:
> +  compatible:
> +    enum:
> +      - loongson,la264
> +      - loongson,la364
> +
> +  reg:
> +    maxItems: 1
> +
> +  device_type: true
> +
> +  clock-frequency:
> +    description: The frequency of cpu in Hz.
> +
> +  model:
> +    $ref: /schemas/types.yaml#/definitions/string
> +    description: User-visible cpu name in /proc/cpuinfo.

First, aren't you mixing nodes?
Second, it is derived from compatible, so no need for such property.

> +
> +required:
> +  - compatible
> +  - reg
> +  - clock-frequency
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    cpus {
> +        #size-cells = <0>;
> +        #address-cells = <1>;
> +
> +        model = "Loongson-2K1000";

Drop, not related.

Best regards,
Krzysztof

Re: [PATCH 4/6] LoongArch: DeviceTree for Loongson-2K0500

[Krzysztof Kozlowski]

On 16/06/2023 08:10, Binbin Zhou wrote:
> Add DeviceTree file for Loongson-2K0500 processor, which integrates one
> 64-bit dual emission superscalar LA264 processor core.
> 
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

Keep subject prefixes with existing style, so: "loongarch: dts:"

> ---
>  arch/loongarch/boot/dts/Makefile            |   2 +
>  arch/loongarch/boot/dts/loongson_2k0500.dts | 311 ++++++++++++++++++++
>  2 files changed, 313 insertions(+)
>  create mode 100644 arch/loongarch/boot/dts/loongson_2k0500.dts
> 
> diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
> index 1e24cdb5180a..0e5ed373b1b4 100644
> --- a/arch/loongarch/boot/dts/Makefile
> +++ b/arch/loongarch/boot/dts/Makefile
> @@ -1,3 +1,5 @@
>  # SPDX-License-Identifier: GPL-2.0-only
>  
> +dtb-$(CONFIG_MACH_LOONGSON64)	= loongson_2k0500.dtb
> +
>  obj-$(CONFIG_BUILTIN_DTB)	+= $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
> diff --git a/arch/loongarch/boot/dts/loongson_2k0500.dts b/arch/loongarch/boot/dts/loongson_2k0500.dts
> new file mode 100644
> index 000000000000..4f58f7b06445
> --- /dev/null
> +++ b/arch/loongarch/boot/dts/loongson_2k0500.dts
> @@ -0,0 +1,311 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +	model = "LS2K0500 Reference Board";
> +	compatible = "loongson,ls2k0500";

Incorrect compatible. This is board, not SoC.

> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		ethernet0 = &gmac0;
> +		ethernet1 = &gmac1;
> +		serial0 = &cpu_uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +		bootargs = "earlycon";

Drop bootargs. Not relevant to mainline.

> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		model = "Loongson-2K0500";

Does not match your bindings.

It does not look like you tested the DTS against bindings. Please run
`make dtbs_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).

> +
> +		cpu0: cpu@0 {
> +			compatible = "loongson,la264";
> +			device_type = "cpu";
> +			reg = <0x0>;
> +			clock-frequency = <500000000>;	/* 500MHz */
> +		};
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +			};
> +		};
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */
> +		      <0x00000000 0x90000000 0x00000000 0x60000000>;
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		linux,cma {
> +			compatible = "shared-dma-pool";
> +			reusable;
> +			size = <0x00000000 0x02000000>;
> +			linux,cma-default;
> +		};
> +	};
> +
> +	ref_100m: clock-ref-100m {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +		clock-output-names = "ref_100m";
> +	};
> +
> +	cpuintc: interrupt-controller {
> +		#interrupt-cells = <1>;
> +		interrupt-controller;
> +		compatible = "loongson,cpu-interrupt-controller";

compatible is always the first property.

> +	};
> +

Missing soc node.

> +	liointc0: interrupt-controller@1fe11400 {
> +		compatible = "loongson,liointc-2.0";
> +		reg = <0 0x1fe11400 0 0x40>,
> +		      <0 0x1fe11040 0 0x8>;
> +		reg-names = "main", "isr0";
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&cpuintc>;
> +		interrupts = <2>;
> +		interrupt-names = "int0";
> +		loongson,parent_int_map = <0xffffffff>, /* int0 */
> +					  <0x00000000>, /* int1 */
> +					  <0x00000000>, /* int2 */
> +					  <0x00000000>; /* int3 */
> +	};
> +
> +	liointc1: interrupt-controller@1fe11440 {
> +		compatible = "loongson,liointc-2.0";
> +		reg = <0 0x1fe11440 0 0x40>,
> +		      <0 0x1fe11048 0 0x8>;
> +		reg-names = "main", "isr0";
> +		interrupt-controller;
> +		#interrupt-cells = <2>;
> +		interrupt-parent = <&cpuintc>;
> +		interrupts = <4>;
> +		interrupt-names = "int2";
> +
> +		loongson,parent_int_map = <0x00000000>, /* int0 */
> +					  <0x00000000>, /* int1 */
> +					  <0xffffffff>, /* int2 */
> +					  <0x00000000>; /* int3 */
> +	};
> +
> +	eiointc: interrupt-controller@1fe11600 {
> +		compatible = "loongson,ls2k0500-eiointc";
> +		interrupt-controller;
> +		#interrupt-cells = <1>;
> +		interrupt-parent = <&cpuintc>;
> +		interrupts = <3>;
> +	};
> +
> +	soc {

Oh, here it is. All MMIO nodes are part of SoC node, not top-level. You
did not check for warnings, right?

Be sure you do not introduce any new W=1 warnings (make dtbs).

Anyway, this is SoC, right? So it should be in DTSI. Don't mix boards
(DTS) and SoCs (DTSI).

> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +
> +		ranges = <0 0x10000000 0 0x10000000 0 0x10000000>,
> +			 <0 0x2000000  0 0x2000000  0 0x2000000>,
> +			 <0 0x20000000 0 0x20000000 0 0x10000000>,
> +			 <0 0x40000000 0 0x40000000 0 0x40000000>,
> +			 <0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
> +
> +		reboot {

And this is not part of SoC. You don't have here reg.

> +			compatible = "syscon-reboot";
> +			regmap = <&pmc>;
> +			offset = <0x30>;
> +			mask = <0x1>;

How does it even work? offset of what? Did you even test it?

> +		};
> +
> +		poweroff {
> +			compatible = "syscon-poweroff";
> +			regmap = <&pmc>;
> +			offset = <0x14>;
> +			mask = <0x3c00>;
> +			value = <0x3c00>;
> +		};
> +
> +		gmac0: ethernet@1f020000 {
> +			compatible = "snps,dwmac-3.70a";
> +			reg = <0 0x1f020000 0 0x10000>;
> +			interrupt-parent = <&liointc0>;
> +			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "macirq";
> +			mac-address = [ 64 48 48 48 48 60 ];/* [>mac 64:48:48:48:48:60 <]*/

Yep, because all boards in the world will come with exactly this one MAC
address. Drop.

> +			phy-mode = "rgmii";
> +			bus_id = <0x0>;
> +		};
> +
> +		gmac1: ethernet@1f030000 {
> +			compatible = "snps,dwmac-3.70a";
> +			reg = <0 0x1f030000 0 0x10000>;
> +			interrupt-parent = <&liointc0>;
> +			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "macirq";
> +			mac-address = [ 64 48 48 48 48 61 ];/* [>mac 64:48:48:48:48:61 <]*/

Drop.

> +			phy-mode = "rgmii";
> +			bus_id = <0x1>;
> +		};
> +
> +		sata@1f040000 {
> +			compatible = "snps,spear-ahci";
> +			reg = <0 0x1f040000 0 0x10000>;
> +			interrupt-parent = <&eiointc>;
> +			interrupts = <75>;
> +		};
> +
> +		ehci@1f050000 {
> +			compatible = "generic-ehci";
> +			reg = <0 0x1f050000 0 0x8000>;
> +			interrupt-parent = <&eiointc>;
> +			interrupts = <71>;
> +		};
> +
> +		ohci@1f058000 {
> +			compatible = "generic-ohci";
> +			reg = <0 0x1f058000 0 0x8000>;
> +			interrupt-parent = <&eiointc>;
> +			interrupts = <72>;
> +		};
> +
> +		clk: clock-controller@1fe10400 {
> +			compatible = "loongson,ls2k-clk";
> +			reg = <0 0x1fe00400 0 0x30>;
> +			#clock-cells = <1>;
> +			clocks = <&ref_100m>;
> +			clock-names = "ref_100m";
> +			status = "disabled";
> +		};
> +
> +		cpu_uart0: serial@1ff40800 {
> +			compatible = "ns16550a";
> +			reg = <0 0x1ff40800 0 0x10>;
> +			clock-frequency = <100000000>;
> +			interrupt-parent = <&eiointc>;
> +			interrupts = <2>;
> +			no-loopback-test;
> +		};
> +
> +		i2c@1ff48000 {
> +			compatible = "loongson,ls2k-i2c";
> +			reg = <0 0x1ff48000 0 0x0800>;
> +			interrupt-parent = <&eiointc>;
> +			interrupts = <14>;
> +
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			eeprom@57 {
> +				compatible = "atmel,24c16";

Are you sure eeprom is part of SoC? Again, aren't you mixing them?

> +				reg = <0x57>;
> +				pagesize = <16>;
> +			};
> +		};
> +
> +		i2c@1ff48800 {
> +			compatible = "loongson,ls2k-i2c";
> +			reg = <0 0x1ff48800 0 0x0800>;
> +			interrupt-parent = <&eiointc>;
> +			interrupts = <15>;
> +			status = "disabled";
> +		};
> +
> +		i2c@1ff49000 {
> +			compatible = "loongson,ls2k-i2c";
> +			reg = <0 0x1ff49000 0 0x0800>;
> +			interrupt-parent = <&eiointc>;
> +			interrupts = <16>;
> +			status = "disabled";
> +		};
> +
> +		i2c@1ff49800 {
> +			compatible = "loongson,ls2k-i2c";
> +			reg = <0 0x1ff49800 0 0x0800>;
> +			interrupt-parent = <&eiointc>;
> +			interrupts = <17>;
> +			status = "disabled";
> +		};
> +
> +		pixi2c@1ff4a000 {
> +			compatible = "loongson,ls2k-i2c";
> +			reg = <0 0x1ff4a000 0 0x0800>;
> +			interrupt-parent = <&eiointc>;
> +			interrupts = <18>;
> +			status = "disabled";
> +		};
> +
> +		pixi2c@1ff4a800 {
> +			compatible = "loongson,ls2k-i2c";
> +			reg = <0 0x1ff4a800 0 0x0800>;
> +			interrupt-parent = <&eiointc>;
> +			interrupts = <19>;
> +			status = "disabled";
> +		};
> +
> +		pmc: acpi@1ff6c000 {
> +			compatible = "syscon";
> +			reg = <0x0 0x1ff6c000 0x0 0x58>;
> +			interrupt-parent = <&eiointc>;
> +			interrupts = <56>;
> +			suspend-address = <0x1c000500>;
> +		};
> +
> +		pcie@16800000 {
> +			compatible = "loongson,ls2k-pci";
> +			device_type = "pci";
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +
> +			reg = <0 0x1a000000 0 0x02000000>,
> +			      <0xfe 0x00000000 0 0x20000000>;
> +
> +			ranges = <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>,
> +				 <0x01000000 0 0x00004000 0 0x16404000 0x0 0x4000>;
> +
> +			pci_bridge@0,0 {

No underscores in node names.

Node names should be generic. See also explanation and list of examples
in DT specification:
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

> +				compatible = "pci0014,1a05.1",
> +					     "pci0014,1a05",
> +					     "pciclass,060400",
> +					     "pciclass,0604";
> +
> +				reg = <0x0000 0x0 0x0 0x0 0x0>;
> +				interrupts = <81>;
> +				interrupt-parent = <&eiointc>;
> +				#interrupt-cells = <1>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 0 &eiointc 81>;
> +			};
> +
> +			pci_bridge@1,0 {

Ditto

> +				compatible = "pci0014,1a05.1",
> +					     "pci0014,1a05",
> +					     "pciclass,060400",
> +					     "pciclass,0604";
> +
> +				reg = <0x0800 0x0 0x0 0x0 0x0>;
> +				interrupts = <82>;
> +				interrupt-parent = <&eiointc>;
> +				#interrupt-cells = <1>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 0 &eiointc 82>;
> +			};
> +		};
> +	};
> +};

Best regards,
Krzysztof

Re: [PATCH 5/6] LoongArch: DeviceTree for Loongson-2K1000

[Krzysztof Kozlowski]

On 16/06/2023 08:11, Binbin Zhou wrote:
> Add DeviceTree file for Loongson-2K1000 processor, which integrates two
> 64-bit dual emission superscalar LA264 processor cores.
> 
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
>  arch/loongarch/boot/dts/Makefile            |   3 +-
>  arch/loongarch/boot/dts/loongson_2k1000.dts | 565 ++++++++++++++++++++
>  2 files changed, 567 insertions(+), 1 deletion(-)
>  create mode 100644 arch/loongarch/boot/dts/loongson_2k1000.dts
> 
> diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
> index 0e5ed373b1b4..c0464bb8e430 100644
> --- a/arch/loongarch/boot/dts/Makefile
> +++ b/arch/loongarch/boot/dts/Makefile
> @@ -1,5 +1,6 @@
>  # SPDX-License-Identifier: GPL-2.0-only
>  
> -dtb-$(CONFIG_MACH_LOONGSON64)	= loongson_2k0500.dtb
> +dtb-$(CONFIG_MACH_LOONGSON64)	= loongson_2k0500.dtb \
> +				  loongson_2k1000.dtb
>  
>  obj-$(CONFIG_BUILTIN_DTB)	+= $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
> diff --git a/arch/loongarch/boot/dts/loongson_2k1000.dts b/arch/loongarch/boot/dts/loongson_2k1000.dts
> new file mode 100644
> index 000000000000..9fd9d400d97f
> --- /dev/null
> +++ b/arch/loongarch/boot/dts/loongson_2k1000.dts
> @@ -0,0 +1,565 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/clock/loongson,ls2k-clk.h>
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> +	model = "LS2K1000 Reference Board";
> +	compatible = "loongson,ls2k1000";
> +

All the same comments apply here. Don't mix SoC (DTSI) with boards.

It does not look like you tested the DTS against bindings. Please run
`make dtbs_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).

Best regards,
Krzysztof

Re: [PATCH 4/6] LoongArch: DeviceTree for Loongson-2K0500

[Krzysztof Kozlowski]

On 16/06/2023 08:10, Binbin Zhou wrote:
> Add DeviceTree file for Loongson-2K0500 processor, which integrates one
> 64-bit dual emission superscalar LA264 processor core.
> 
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---


> +
> +		pixi2c@1ff4a800 {
> +			compatible = "loongson,ls2k-i2c";
> +			reg = <0 0x1ff4a800 0 0x0800>;
> +			interrupt-parent = <&eiointc>;
> +			interrupts = <19>;
> +			status = "disabled";
> +		};
> +
> +		pmc: acpi@1ff6c000 {
> +			compatible = "syscon";

One more - this is not allowed and clear NAK.

Best regards,
Krzysztof

Re: [PATCH 1/6] dt-bindings: loongarch: Add CPU bindings for LoongArch

[Binbin Zhou]

On Fri, Jun 16, 2023 at 5:34 PM Conor Dooley <conor.dooley@microchip.com> wrote:
>
> On Fri, Jun 16, 2023 at 02:10:38PM +0800, Binbin Zhou wrote:
> > Add the available CPUs in LoongArch binding with DT schema format using
> > json-schema.
> >
> > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > ---
> >  .../devicetree/bindings/loongarch/cpus.yaml   | 65 +++++++++++++++++++
> >  1 file changed, 65 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> > new file mode 100644
> > index 000000000000..c3e2dba42c81
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> > @@ -0,0 +1,65 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: LoongArch CPUs
> > +
> > +maintainers:
> > +  - Binbin Zhou <zhoubinbin@loongson.cn>
> > +
> > +description:
> > +  The device tree allows to describe the layout of CPUs in a system through
> > +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> > +  defining properties for every CPU.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - loongson,la264
> > +      - loongson,la364
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  device_type: true
> > +
> > +  clock-frequency:
> > +    description: The frequency of cpu in Hz.
>
> Why don't you just add a ref to the common cpu schema and use the
> standard properties for communicating clock frequencies?
> You then get the standard properties for l1 caches, power management,
> frequency scaling etc as a side effect.

Hi Conor:

Sorry, not sure if I understand correctly. Do the standard attributes
refer to the following:

power-domains = <>
clocks = <>
i-cache-size = <>
d-cache-size = <>
next-level-cache = <>

Thanks.
Binbin

>
> Cheers,
> Conor.

Re: [PATCH 1/6] dt-bindings: loongarch: Add CPU bindings for LoongArch

[Binbin Zhou]

On Fri, Jun 16, 2023 at 5:51 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 16/06/2023 08:10, Binbin Zhou wrote:
> > Add the available CPUs in LoongArch binding with DT schema format using
> > json-schema.
> >
> > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > ---
> >  .../devicetree/bindings/loongarch/cpus.yaml   | 65 +++++++++++++++++++
> >  1 file changed, 65 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> > new file mode 100644
> > index 000000000000..c3e2dba42c81
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
> > @@ -0,0 +1,65 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: LoongArch CPUs
> > +
> > +maintainers:
> > +  - Binbin Zhou <zhoubinbin@loongson.cn>
> > +
> > +description:
> > +  The device tree allows to describe the layout of CPUs in a system through
> > +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
> > +  defining properties for every CPU.
>
> I understand you copied it from ARM, but I would prefer to have here
> something meaningful. Bindings description does not explain what is DTS,
> but explains what the hardware is.

Hi Krzysztof:

I am very sorry, this is my problem and I will rewrite this part.

>
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - loongson,la264
> > +      - loongson,la364
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  device_type: true
> > +
> > +  clock-frequency:
> > +    description: The frequency of cpu in Hz.
> > +
> > +  model:
> > +    $ref: /schemas/types.yaml#/definitions/string
> > +    description: User-visible cpu name in /proc/cpuinfo.
>
> First, aren't you mixing nodes?
> Second, it is derived from compatible, so no need for such property.

Well, this attribute is an attempt to tweak it.

As the description says, this attribute was added to show the model
name in /proc/cpuinfo. here, we will show the custom name instead of
using the cpu core name directly.

For example, on a Loongson-3A5000 machine, although its cpu core is
la464, we can see:
[root@fedora ~]# cat /proc/cpuinfo
system type : generic-loongson-machine
..............
Model Name : Loongson-3A5000-HV
............
CPU MHz : 2500.00
...........

Unfortunately, some Loongson-2K chips are not designed with
corresponding CPUNAME registers, so we expect to add them in the DTS.

At first, we considered writing it directly into cpu compatible, but
it seems that dts compatible is all lower case, while our desired
model name contains upper case letters.

What do you think if we repositioned this attribute under cpu?

                cpu0: cpu@0 {
                        compatible = "loongson,la264".
                        model = "Loongson-2K1000".
                        device_type = "cpu".
                        reg= <0x0>.
                        .....
                }.

>
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clock-frequency
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    cpus {
> > +        #size-cells = <0>;
> > +        #address-cells = <1>;
> > +
> > +        model = "Loongson-2K1000";
>
> Drop, not related.
>
> Best regards,
> Krzysztof
>

Re: [PATCH 5/6] LoongArch: DeviceTree for Loongson-2K1000

[Binbin Zhou]

On Fri, Jun 16, 2023 at 5:48 PM Conor Dooley <conor.dooley@microchip.com> wrote:
>
> On Fri, Jun 16, 2023 at 02:11:31PM +0800, Binbin Zhou wrote:
>
> > +     memalloc@0 {
> > +             compatible = "loongson,ls-memalloc";
> > +             reg = <0 0x90000000 0 0x20000000>;
> > +     };
>
> This is not documented.

Hi Conor:

Sorry, this is my mistake, a private driver will use it, I will try to
remove it in the next version.

>
> > +             gpio0: gpio@1fe00500 {
> > +                     compatible = "loongson,ls2k-gpio", "syscon";
>
> This isn't valid either, the binding doesn't allow syscon?

The syscon is not needed right now. I will remove it.

>
> > +                     ethernet@3,1 {
> > +                             compatible = "pci0014,7a03.0",
> > +                                          "pci0014,7a03",
> > +                                          "pciclass,020000",
> > +                                          "pciclass,0200",
> > +                                          "loongson, pci-gmac";
>
> None of the compatibles from here on out are documented either.

These are required to be added according to DeviceTree Spec PCI [1],
Linux does not use these compatible for now.
Removing them really doesn't affect the driver, but to follow the spec
and make sure every node has a compatible, I've left them all in.

Are they not required?

[1]: https://www.openfirmware.info/data/docs/bus.pci.pdf

Thanks.
Binbin

>
> Cheers,
> Conor.

Re: [PATCH 5/6] LoongArch: DeviceTree for Loongson-2K1000

[Binbin Zhou]

On Fri, Jun 16, 2023 at 5:59 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 16/06/2023 08:11, Binbin Zhou wrote:
> > Add DeviceTree file for Loongson-2K1000 processor, which integrates two
> > 64-bit dual emission superscalar LA264 processor cores.
> >
> > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > ---
> >  arch/loongarch/boot/dts/Makefile            |   3 +-
> >  arch/loongarch/boot/dts/loongson_2k1000.dts | 565 ++++++++++++++++++++
> >  2 files changed, 567 insertions(+), 1 deletion(-)
> >  create mode 100644 arch/loongarch/boot/dts/loongson_2k1000.dts
> >
> > diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
> > index 0e5ed373b1b4..c0464bb8e430 100644
> > --- a/arch/loongarch/boot/dts/Makefile
> > +++ b/arch/loongarch/boot/dts/Makefile
> > @@ -1,5 +1,6 @@
> >  # SPDX-License-Identifier: GPL-2.0-only
> >
> > -dtb-$(CONFIG_MACH_LOONGSON64)        = loongson_2k0500.dtb
> > +dtb-$(CONFIG_MACH_LOONGSON64)        = loongson_2k0500.dtb \
> > +                               loongson_2k1000.dtb
> >
> >  obj-$(CONFIG_BUILTIN_DTB)    += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
> > diff --git a/arch/loongarch/boot/dts/loongson_2k1000.dts b/arch/loongarch/boot/dts/loongson_2k1000.dts
> > new file mode 100644
> > index 000000000000..9fd9d400d97f
> > --- /dev/null
> > +++ b/arch/loongarch/boot/dts/loongson_2k1000.dts
> > @@ -0,0 +1,565 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/clock/loongson,ls2k-clk.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +
> > +/ {
> > +     model = "LS2K1000 Reference Board";
> > +     compatible = "loongson,ls2k1000";
> > +
>
> All the same comments apply here. Don't mix SoC (DTSI) with boards.

Hi Krzysztof:

I'm very sorry, this is the first time I've written a full DTS.
Do you mean that I need to put the descriptions of these devices into
DTSI and the descriptions of the boards into DTS?

>
> It does not look like you tested the DTS against bindings. Please run
> `make dtbs_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).

Ok, I will do these checks before the next version.

Thanks.
Binbin

>
> Best regards,
> Krzysztof
>

Re: [PATCH 5/6] LoongArch: DeviceTree for Loongson-2K1000

[Krzysztof Kozlowski]

On 17/06/2023 08:59, Binbin Zhou wrote:
> On Fri, Jun 16, 2023 at 5:59 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 16/06/2023 08:11, Binbin Zhou wrote:
>>> Add DeviceTree file for Loongson-2K1000 processor, which integrates two
>>> 64-bit dual emission superscalar LA264 processor cores.
>>>
>>> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
>>> ---
>>>  arch/loongarch/boot/dts/Makefile            |   3 +-
>>>  arch/loongarch/boot/dts/loongson_2k1000.dts | 565 ++++++++++++++++++++
>>>  2 files changed, 567 insertions(+), 1 deletion(-)
>>>  create mode 100644 arch/loongarch/boot/dts/loongson_2k1000.dts
>>>
>>> diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
>>> index 0e5ed373b1b4..c0464bb8e430 100644
>>> --- a/arch/loongarch/boot/dts/Makefile
>>> +++ b/arch/loongarch/boot/dts/Makefile
>>> @@ -1,5 +1,6 @@
>>>  # SPDX-License-Identifier: GPL-2.0-only
>>>
>>> -dtb-$(CONFIG_MACH_LOONGSON64)        = loongson_2k0500.dtb
>>> +dtb-$(CONFIG_MACH_LOONGSON64)        = loongson_2k0500.dtb \
>>> +                               loongson_2k1000.dtb
>>>
>>>  obj-$(CONFIG_BUILTIN_DTB)    += $(addsuffix .dtb.o, $(CONFIG_BUILTIN_DTB_NAME))
>>> diff --git a/arch/loongarch/boot/dts/loongson_2k1000.dts b/arch/loongarch/boot/dts/loongson_2k1000.dts
>>> new file mode 100644
>>> index 000000000000..9fd9d400d97f
>>> --- /dev/null
>>> +++ b/arch/loongarch/boot/dts/loongson_2k1000.dts
>>> @@ -0,0 +1,565 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include <dt-bindings/interrupt-controller/irq.h>
>>> +#include <dt-bindings/clock/loongson,ls2k-clk.h>
>>> +#include <dt-bindings/gpio/gpio.h>
>>> +
>>> +/ {
>>> +     model = "LS2K1000 Reference Board";
>>> +     compatible = "loongson,ls2k1000";
>>> +
>>
>> All the same comments apply here. Don't mix SoC (DTSI) with boards.
> 
> Hi Krzysztof:
> 
> I'm very sorry, this is the first time I've written a full DTS.
> Do you mean that I need to put the descriptions of these devices into
> DTSI and the descriptions of the boards into DTS?

You need to clearly identify what is SoC and what is board. Just look
for every arm/arm64/riscv example. SoC relevant properties go to SoC
DTSI. Board relevant properties go to board DTS.

Best regards,
Krzysztof

Re: [PATCH 1/6] dt-bindings: loongarch: Add CPU bindings for LoongArch

[Krzysztof Kozlowski]

On 17/06/2023 08:31, Binbin Zhou wrote:
> On Fri, Jun 16, 2023 at 5:51 PM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 16/06/2023 08:10, Binbin Zhou wrote:
>>> Add the available CPUs in LoongArch binding with DT schema format using
>>> json-schema.
>>>
>>> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
>>> ---
>>>  .../devicetree/bindings/loongarch/cpus.yaml   | 65 +++++++++++++++++++
>>>  1 file changed, 65 insertions(+)
>>>  create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
>>> new file mode 100644
>>> index 000000000000..c3e2dba42c81
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
>>> @@ -0,0 +1,65 @@
>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: LoongArch CPUs
>>> +
>>> +maintainers:
>>> +  - Binbin Zhou <zhoubinbin@loongson.cn>
>>> +
>>> +description:
>>> +  The device tree allows to describe the layout of CPUs in a system through
>>> +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>>> +  defining properties for every CPU.
>>
>> I understand you copied it from ARM, but I would prefer to have here
>> something meaningful. Bindings description does not explain what is DTS,
>> but explains what the hardware is.
> 
> Hi Krzysztof:
> 
> I am very sorry, this is my problem and I will rewrite this part.
> 
>>
>>> +
>>> +properties:
>>> +  compatible:
>>> +    enum:
>>> +      - loongson,la264
>>> +      - loongson,la364
>>> +
>>> +  reg:
>>> +    maxItems: 1
>>> +
>>> +  device_type: true
>>> +
>>> +  clock-frequency:
>>> +    description: The frequency of cpu in Hz.
>>> +
>>> +  model:
>>> +    $ref: /schemas/types.yaml#/definitions/string
>>> +    description: User-visible cpu name in /proc/cpuinfo.
>>
>> First, aren't you mixing nodes?
>> Second, it is derived from compatible, so no need for such property.
> 
> Well, this attribute is an attempt to tweak it.
> 
> As the description says, this attribute was added to show the model
> name in /proc/cpuinfo. here, we will show the custom name instead of
> using the cpu core name directly.

DTS is not some translation layer. You can decode compatible and put
into /proc/cpuinfo whatever you wish.

> 
> For example, on a Loongson-3A5000 machine, although its cpu core is
> la464, we can see:
> [root@fedora ~]# cat /proc/cpuinfo
> system type : generic-loongson-machine
> ..............
> Model Name : Loongson-3A5000-HV
> ............
> CPU MHz : 2500.00
> ...........
> 
> Unfortunately, some Loongson-2K chips are not designed with
> corresponding CPUNAME registers, so we expect to add them in the DTS.
> 
> At first, we considered writing it directly into cpu compatible, but
> it seems that dts compatible is all lower case, while our desired
> model name contains upper case letters.
> 
> What do you think if we repositioned this attribute under cpu?

You already did it, so about which solution we talk about?

Anyway, I am against store translation of compatibles in DTS.

Best regards,
Krzysztof

Re: [PATCH 5/6] LoongArch: DeviceTree for Loongson-2K1000

[Krzysztof Kozlowski]

On 17/06/2023 08:53, Binbin Zhou wrote:
> 
>>
>>> +                     ethernet@3,1 {
>>> +                             compatible = "pci0014,7a03.0",
>>> +                                          "pci0014,7a03",
>>> +                                          "pciclass,020000",
>>> +                                          "pciclass,0200",
>>> +                                          "loongson, pci-gmac";
>>
>> None of the compatibles from here on out are documented either.
> 
> These are required to be added according to DeviceTree Spec PCI [1],
> Linux does not use these compatible for now.
> Removing them really doesn't affect the driver, but to follow the spec
> and make sure every node has a compatible, I've left them all in.
> 
> Are they not required?

If it passes dtbs_check, they can stay.

Best regards,
Krzysztof

Re: [PATCH 1/6] dt-bindings: loongarch: Add CPU bindings for LoongArch

[Conor Dooley]

On 17 June 2023 07:29:06 IST, Binbin Zhou <zhoubb.aaron@gmail.com> wrote:
>On Fri, Jun 16, 2023 at 5:34 PM Conor Dooley <conor.dooley@microchip.com> wrote:
>>
>> On Fri, Jun 16, 2023 at 02:10:38PM +0800, Binbin Zhou wrote:
>> > Add the available CPUs in LoongArch binding with DT schema format using
>> > json-schema.
>> >
>> > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
>> > ---
>> >  .../devicetree/bindings/loongarch/cpus.yaml   | 65 +++++++++++++++++++
>> >  1 file changed, 65 insertions(+)
>> >  create mode 100644 Documentation/devicetree/bindings/loongarch/cpus.yaml
>> >
>> > diff --git a/Documentation/devicetree/bindings/loongarch/cpus.yaml b/Documentation/devicetree/bindings/loongarch/cpus.yaml
>> > new file mode 100644
>> > index 000000000000..c3e2dba42c81
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/loongarch/cpus.yaml
>> > @@ -0,0 +1,65 @@
>> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> > +%YAML 1.2
>> > +---
>> > +$id: http://devicetree.org/schemas/loongarch/cpus.yaml#
>> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> > +
>> > +title: LoongArch CPUs
>> > +
>> > +maintainers:
>> > +  - Binbin Zhou <zhoubinbin@loongson.cn>
>> > +
>> > +description:
>> > +  The device tree allows to describe the layout of CPUs in a system through
>> > +  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
>> > +  defining properties for every CPU.
>> > +
>> > +properties:
>> > +  compatible:
>> > +    enum:
>> > +      - loongson,la264
>> > +      - loongson,la364
>> > +
>> > +  reg:
>> > +    maxItems: 1
>> > +
>> > +  device_type: true
>> > +
>> > +  clock-frequency:
>> > +    description: The frequency of cpu in Hz.
>>
>> Why don't you just add a ref to the common cpu schema and use the
>> standard properties for communicating clock frequencies?
>> You then get the standard properties for l1 caches, power management,
>> frequency scaling etc as a side effect.
>
>Hi Conor:
>
>Sorry, not sure if I understand correctly. Do the standard attributes
>refer to the following:
>
>power-domains = <>
>clocks = <>
>i-cache-size = <>
>d-cache-size = <>
>next-level-cache = <>

Yes, those are the sort of things I meant.

Cheers,
Conor.