* [PATCH v8 0/2] pwm: Introduce pwm driver for the Loongson family chips @ 2024-12-10 12:37 Binbin Zhou 2024-12-10 12:37 ` [PATCH v8 1/2] dt-bindings: pwm: Add Loongson PWM controller Binbin Zhou 2024-12-10 12:37 ` [PATCH v8 2/2] pwm: Add Loongson PWM controller support Binbin Zhou 0 siblings, 2 replies; 7+ messages in thread From: Binbin Zhou @ 2024-12-10 12:37 UTC (permalink / raw) To: Binbin Zhou, Huacai Chen, Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Juxin Gao Cc: Huacai Chen, linux-pwm, devicetree, Xuerui Wang, loongarch, Binbin Zhou [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #1: Type: text/plain; charset=a, Size: 3475 bytes --] Hi all: This patchset introduce a generic PWM framework driver for Loongson family. Each PWM has one pulse width output signal and one pulse input signal to be measured. It can be found on Loongson-2K series cpus and Loongson LS7A bridge chips. Thanks. ------- V8: patch (2/2): - Rebase on pwm/for-next; - Drop inappropriate comments in “Limitations”; - Drop HZ_PER_KHZ for readability; - NANOHZ_PER_HZ -> NSEC_PER_SEC; - Rewrite the clk fetch section to look more flexible and not have to care about ACPI or DT; - Add explicit initialization of the CTRL register in probe(). Link to V7: https://lore.kernel.org/all/cover.1729583747.git.zhoubinbin@loongson.cn/ V7: Thanks for Sean's advice. patch (2/2): - Set chip->atomic to keep pwm_apply_atomic() can be used with the pwm. - Test with CONFIG_PWM_DEBUG and CONFIG_DEBUG_ATOMIC_SLEEP enabled. Link to V6: https://lore.kernel.org/all/cover.1728463622.git.zhoubinbin@loongson.cn/ V6: patch (2/2): - Rebase on pwm/for-next; - Add Reference Manual; - Shortcut if !pwm->state.enabled; - When state->enabled is true, unconditionally execute pwm_loongson_set_polarity() to avoid that the polarity register is not set correctly. Link to V5: https://lore.kernel.org/all/cover.1720516327.git.zhoubinbin@loongson.cn/ V5: patch (2/2): - Rebase on pwm/for-next; - Test with PWM_DEBUG enabled. - In pwm_loongson_apply(), the pwm state is determined before the pwm polarity, avoid test failures when PWM_DEBUG is enabled; - Added DIV64_U64_ROUND_UP in pwm_loongson_get_state() to avoid precision loss and to avoid test failures when PWM_DEBUG is enabled. Link to V4: https://lore.kernel.org/all/cover.1716795485.git.zhoubinbin@loongson.cn/ V4: patch (2/2): - Rebase on pwm/for-next; - Addressed Uwe's review comments: - Make use of devm_pwmchip_alloc() function; - Add Limitations description; - Add LOONGSON_ prefix for Loongson pwm register defines; - Keep regs written only once; - Rewrite duty/period calculation; - Add dev_err_probe() in .probe(); - Fix some code style. Link to V3: https://lore.kernel.org/linux-pwm/cover.1713164810.git.zhoubinbin@loongson.cn/ V3: patch (1/2): - Add Reviewed-by tag from Krzysztof, thanks. patch (2/2): - Several code stlye adjustments, such as line breaks. Link to V2: https://lore.kernel.org/all/cover.1712732719.git.zhoubinbin@loongson.cn/ v2: - Remove the dts-related patches and update dts at once after all relevant drivers are complete. patch (1/2): - The dt-binding filename should match compatible, rename it as loongson,ls7a-pwm.yaml; - Update binding description; - Add description for each pwm cell; - Drop '#pwm-cells' from required, for pwm.yaml makes it required already. Link to v1: https://lore.kernel.org/linux-pwm/cover.1711953223.git.zhoubinbin@loongson.cn/ Binbin Zhou (2): dt-bindings: pwm: Add Loongson PWM controller pwm: Add Loongson PWM controller support .../bindings/pwm/loongson,ls7a-pwm.yaml | 66 ++++ MAINTAINERS | 7 + drivers/pwm/Kconfig | 12 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-loongson.c | 296 ++++++++++++++++++ 5 files changed, 382 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml create mode 100644 drivers/pwm/pwm-loongson.c base-commit: 483082d78a092a3c1f343a76a2edb196069b4092 -- 2.43.5 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v8 1/2] dt-bindings: pwm: Add Loongson PWM controller 2024-12-10 12:37 [PATCH v8 0/2] pwm: Introduce pwm driver for the Loongson family chips Binbin Zhou @ 2024-12-10 12:37 ` Binbin Zhou 2024-12-10 12:37 ` [PATCH v8 2/2] pwm: Add Loongson PWM controller support Binbin Zhou 1 sibling, 0 replies; 7+ messages in thread From: Binbin Zhou @ 2024-12-10 12:37 UTC (permalink / raw) To: Binbin Zhou, Huacai Chen, Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Juxin Gao Cc: Huacai Chen, linux-pwm, devicetree, Xuerui Wang, loongarch, Binbin Zhou, Krzysztof Kozlowski Add Loongson PWM controller binding with DT schema format using json-schema. Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Huacai Chen <chenhuacai@loongson.cn> --- .../bindings/pwm/loongson,ls7a-pwm.yaml | 66 +++++++++++++++++++ MAINTAINERS | 6 ++ 2 files changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml b/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml new file mode 100644 index 000000000000..46814773e0cc --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/loongson,ls7a-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson PWM Controller + +maintainers: + - Binbin Zhou <zhoubinbin@loongson.cn> + +description: + The Loongson PWM has one pulse width output signal and one pulse input + signal to be measured. + It can be found on Loongson-2K series cpus and Loongson LS7A bridge chips. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + oneOf: + - const: loongson,ls7a-pwm + - items: + - enum: + - loongson,ls2k0500-pwm + - loongson,ls2k1000-pwm + - loongson,ls2k2000-pwm + - const: loongson,ls7a-pwm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + '#pwm-cells': + description: + The first cell must have a value of 0, which specifies the PWM output signal; + The second cell is the period in nanoseconds; + The third cell flag supported by this binding is PWM_POLARITY_INVERTED. + const: 3 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/clock/loongson,ls2k-clk.h> + pwm@1fe22000 { + compatible = "loongson,ls2k1000-pwm", "loongson,ls7a-pwm"; + reg = <0x1fe22000 0x10>; + interrupt-parent = <&liointc0>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk LOONGSON2_APB_CLK>; + #pwm-cells = <3>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 1e930c7a58b1..b876db33126e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13494,6 +13494,12 @@ S: Maintained F: Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml F: drivers/i2c/busses/i2c-ls2x.c +LOONGSON PWM DRIVER +M: Binbin Zhou <zhoubinbin@loongson.cn> +L: linux-pwm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml + LOONGSON-2 SOC SERIES CLOCK DRIVER M: Yinbo Zhu <zhuyinbo@loongson.cn> L: linux-clk@vger.kernel.org -- 2.43.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v8 2/2] pwm: Add Loongson PWM controller support 2024-12-10 12:37 [PATCH v8 0/2] pwm: Introduce pwm driver for the Loongson family chips Binbin Zhou 2024-12-10 12:37 ` [PATCH v8 1/2] dt-bindings: pwm: Add Loongson PWM controller Binbin Zhou @ 2024-12-10 12:37 ` Binbin Zhou 2025-02-10 18:26 ` Uwe Kleine-König 1 sibling, 1 reply; 7+ messages in thread From: Binbin Zhou @ 2024-12-10 12:37 UTC (permalink / raw) To: Binbin Zhou, Huacai Chen, Uwe Kleine-König, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Juxin Gao Cc: Huacai Chen, linux-pwm, devicetree, Xuerui Wang, loongarch, Binbin Zhou This commit adds a generic PWM framework driver for the PWM controller found on Loongson family chips. Co-developed-by: Juxin Gao <gaojuxin@loongson.cn> Signed-off-by: Juxin Gao <gaojuxin@loongson.cn> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn> Acked-by: Huacai Chen <chenhuacai@loongson.cn> --- MAINTAINERS | 1 + drivers/pwm/Kconfig | 12 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-loongson.c | 296 +++++++++++++++++++++++++++++++++++++ 4 files changed, 310 insertions(+) create mode 100644 drivers/pwm/pwm-loongson.c diff --git a/MAINTAINERS b/MAINTAINERS index b876db33126e..ed7a4304da2f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13499,6 +13499,7 @@ M: Binbin Zhou <zhoubinbin@loongson.cn> L: linux-pwm@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pwm/loongson,ls7a-pwm.yaml +F: drivers/pwm/pwm-loongson.c LOONGSON-2 SOC SERIES CLOCK DRIVER M: Yinbo Zhu <zhuyinbo@loongson.cn> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 0915c1e7df16..ef02a44d83a7 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -351,6 +351,18 @@ config PWM_KEEMBAY To compile this driver as a module, choose M here: the module will be called pwm-keembay. +config PWM_LOONGSON + tristate "Loongson PWM support" + depends on MACH_LOONGSON64 || COMPILE_TEST + depends on COMMON_CLK + help + Generic PWM framework driver for Loongson family. + It can be found on Loongson-2K series cpus and Loongson LS7A + bridge chips. + + To compile this driver as a module, choose M here: the module + will be called pwm-loongson. + config PWM_LP3943 tristate "TI/National Semiconductor LP3943 PWM support" depends on MFD_LP3943 diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 9081e0c0e9e0..7c18c9be419f 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_PWM_INTEL_LGM) += pwm-intel-lgm.o obj-$(CONFIG_PWM_IQS620A) += pwm-iqs620a.o obj-$(CONFIG_PWM_JZ4740) += pwm-jz4740.o obj-$(CONFIG_PWM_KEEMBAY) += pwm-keembay.o +obj-$(CONFIG_PWM_LOONGSON) += pwm-loongson.o obj-$(CONFIG_PWM_LP3943) += pwm-lp3943.o obj-$(CONFIG_PWM_LPC18XX_SCT) += pwm-lpc18xx-sct.o obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o diff --git a/drivers/pwm/pwm-loongson.c b/drivers/pwm/pwm-loongson.c new file mode 100644 index 000000000000..2f90eccba0bd --- /dev/null +++ b/drivers/pwm/pwm-loongson.c @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017-2024 Loongson Technology Corporation Limited. + * + * Loongson PWM driver + * + * For Loongson's PWM IP block documentation please refer Chapter 11 of + * Reference Manual: https://loongson.github.io/LoongArch-Documentation/Loongson-7A1000-usermanual-EN.pdf + * + * Author: Juxin Gao <gaojuxin@loongson.cn> + * Further cleanup and restructuring by: + * Binbin Zhou <zhoubinbin@loongson.cn> + * + * Limitations: + * - If both DUTY and PERIOD are set to 0, the output is a constant low signal. + * - When disabled the output is driven to 0 independent of the configured + * polarity. + */ + +#include <linux/acpi.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pwm.h> +#include <linux/units.h> + +/* Loongson PWM registers */ +#define LOONGSON_PWM_REG_DUTY 0x4 /* Low Pulse Buffer Register */ +#define LOONGSON_PWM_REG_PERIOD 0x8 /* Pulse Period Buffer Register */ +#define LOONGSON_PWM_REG_CTRL 0xc /* Control Register */ + +/* Control register bits */ +#define LOONGSON_PWM_CTRL_EN BIT(0) /* Counter Enable Bit */ +#define LOONGSON_PWM_CTRL_OE BIT(3) /* Pulse Output Enable Control Bit, Valid Low */ +#define LOONGSON_PWM_CTRL_SINGLE BIT(4) /* Single Pulse Control Bit */ +#define LOONGSON_PWM_CTRL_INTE BIT(5) /* Interrupt Enable Bit */ +#define LOONGSON_PWM_CTRL_INT BIT(6) /* Interrupt Bit */ +#define LOONGSON_PWM_CTRL_RST BIT(7) /* Counter Reset Bit */ +#define LOONGSON_PWM_CTRL_CAPTE BIT(8) /* Measurement Pulse Enable Bit */ +#define LOONGSON_PWM_CTRL_INVERT BIT(9) /* Output flip-flop Enable Bit */ +#define LOONGSON_PWM_CTRL_DZONE BIT(10) /* Anti-dead Zone Enable Bit */ + +/* default input clk frequency for the ACPI case */ +#define LOONGSON_PWM_FREQ_DEFAULT 50000 /* Hz */ + +struct pwm_loongson_suspend_store { + u32 ctrl; + u32 duty; + u32 period; +}; + +struct pwm_loongson_ddata { + struct clk *clk; + void __iomem *base; + u64 clk_rate; + struct pwm_loongson_suspend_store lss; +}; + +static inline struct pwm_loongson_ddata *to_pwm_loongson_ddata(struct pwm_chip *chip) +{ + return pwmchip_get_drvdata(chip); +} + +static inline u32 pwm_loongson_readl(struct pwm_loongson_ddata *ddata, u32 offset) +{ + return readl(ddata->base + offset); +} + +static inline void pwm_loongson_writel(struct pwm_loongson_ddata *ddata, + u32 val, u32 offset) +{ + writel(val, ddata->base + offset); +} + +static int pwm_loongson_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, + enum pwm_polarity polarity) +{ + u16 val; + struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); + + val = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); + + if (polarity == PWM_POLARITY_INVERSED) + /* Duty cycle defines LOW period of PWM */ + val |= LOONGSON_PWM_CTRL_INVERT; + else + /* Duty cycle defines HIGH period of PWM */ + val &= ~LOONGSON_PWM_CTRL_INVERT; + + pwm_loongson_writel(ddata, val, LOONGSON_PWM_REG_CTRL); + + return 0; +} + +static void pwm_loongson_disable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + u32 val; + struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); + + val = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); + val &= ~LOONGSON_PWM_CTRL_EN; + pwm_loongson_writel(ddata, val, LOONGSON_PWM_REG_CTRL); +} + +static int pwm_loongson_enable(struct pwm_chip *chip, struct pwm_device *pwm) +{ + u32 val; + struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); + + val = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); + val |= LOONGSON_PWM_CTRL_EN; + pwm_loongson_writel(ddata, val, LOONGSON_PWM_REG_CTRL); + + return 0; +} + +static int pwm_loongson_config(struct pwm_chip *chip, struct pwm_device *pwm, + u64 duty_ns, u64 period_ns) +{ + u32 duty, period; + struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); + + /* duty = duty_ns * ddata->clk_rate / NSEC_PER_SEC */ + duty = mul_u64_u64_div_u64(duty_ns, ddata->clk_rate, NSEC_PER_SEC); + pwm_loongson_writel(ddata, duty, LOONGSON_PWM_REG_DUTY); + + /* period = period_ns * ddata->clk_rate / NSEC_PER_SEC */ + period = mul_u64_u64_div_u64(period_ns, ddata->clk_rate, NSEC_PER_SEC); + pwm_loongson_writel(ddata, period, LOONGSON_PWM_REG_PERIOD); + + return 0; +} + +static int pwm_loongson_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + int ret; + u64 period, duty_cycle; + bool enabled = pwm->state.enabled; + + if (!state->enabled) { + if (enabled) + pwm_loongson_disable(chip, pwm); + return 0; + } + + ret = pwm_loongson_set_polarity(chip, pwm, state->polarity); + if (ret) + return ret; + + period = min(state->period, NSEC_PER_SEC); + duty_cycle = min(state->duty_cycle, NSEC_PER_SEC); + + ret = pwm_loongson_config(chip, pwm, duty_cycle, period); + if (ret) + return ret; + + if (!enabled && state->enabled) + ret = pwm_loongson_enable(chip, pwm); + + return ret; +} + +static int pwm_loongson_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + u32 duty, period, ctrl; + struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); + + duty = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_DUTY); + period = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_PERIOD); + ctrl = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); + + /* duty & period have a max of 2^32, so we can't overflow */ + state->duty_cycle = DIV64_U64_ROUND_UP((u64)duty * NSEC_PER_SEC, ddata->clk_rate); + state->period = DIV64_U64_ROUND_UP((u64)period * NSEC_PER_SEC, ddata->clk_rate); + state->polarity = (ctrl & LOONGSON_PWM_CTRL_INVERT) ? PWM_POLARITY_INVERSED : + PWM_POLARITY_NORMAL; + state->enabled = (ctrl & LOONGSON_PWM_CTRL_EN) ? true : false; + + return 0; +} + +static const struct pwm_ops pwm_loongson_ops = { + .apply = pwm_loongson_apply, + .get_state = pwm_loongson_get_state, +}; + +static int pwm_loongson_probe(struct platform_device *pdev) +{ + int ret; + struct pwm_chip *chip; + struct pwm_loongson_ddata *ddata; + struct device *dev = &pdev->dev; + + chip = devm_pwmchip_alloc(dev, 1, sizeof(*ddata)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + ddata = to_pwm_loongson_ddata(chip); + + ddata->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ddata->base)) + return PTR_ERR(ddata->base); + + ddata->clk = devm_clk_get_optional_enabled(dev, NULL); + if (IS_ERR(ddata->clk)) + return dev_err_probe(dev, PTR_ERR(ddata->clk), + "failed to get pwm clock\n"); + if (ddata->clk) { + ret = devm_clk_rate_exclusive_get(dev, ddata->clk); + if (ret) + return ret; + + ddata->clk_rate = clk_get_rate(ddata->clk); + } else { + ddata->clk_rate = LOONGSON_PWM_FREQ_DEFAULT; + } + + /* Explicitly initialize the CTRL register */ + pwm_loongson_writel(ddata, 0, LOONGSON_PWM_REG_CTRL); + + chip->ops = &pwm_loongson_ops; + chip->atomic = true; + dev_set_drvdata(dev, chip); + + ret = devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to add PWM chip\n"); + + return 0; +} + +static int pwm_loongson_suspend(struct device *dev) +{ + struct pwm_chip *chip = dev_get_drvdata(dev); + struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); + + ddata->lss.ctrl = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); + ddata->lss.duty = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_DUTY); + ddata->lss.period = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_PERIOD); + + clk_disable_unprepare(ddata->clk); + + return 0; +} + +static int pwm_loongson_resume(struct device *dev) +{ + int ret; + struct pwm_chip *chip = dev_get_drvdata(dev); + struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); + + ret = clk_prepare_enable(ddata->clk); + if (ret) + return ret; + + pwm_loongson_writel(ddata, ddata->lss.ctrl, LOONGSON_PWM_REG_CTRL); + pwm_loongson_writel(ddata, ddata->lss.duty, LOONGSON_PWM_REG_DUTY); + pwm_loongson_writel(ddata, ddata->lss.period, LOONGSON_PWM_REG_PERIOD); + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(pwm_loongson_pm_ops, pwm_loongson_suspend, + pwm_loongson_resume); + +static const struct of_device_id pwm_loongson_of_ids[] = { + { .compatible = "loongson,ls7a-pwm" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, pwm_loongson_of_ids); + +static const struct acpi_device_id pwm_loongson_acpi_ids[] = { + { "LOON0006" }, + { } +}; +MODULE_DEVICE_TABLE(acpi, pwm_loongson_acpi_ids); + +static struct platform_driver pwm_loongson_driver = { + .probe = pwm_loongson_probe, + .driver = { + .name = "loongson-pwm", + .pm = pm_ptr(&pwm_loongson_pm_ops), + .of_match_table = pwm_loongson_of_ids, + .acpi_match_table = pwm_loongson_acpi_ids, + }, +}; +module_platform_driver(pwm_loongson_driver); + +MODULE_DESCRIPTION("Loongson PWM driver"); +MODULE_AUTHOR("Loongson Technology Corporation Limited."); +MODULE_LICENSE("GPL"); -- 2.43.5 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v8 2/2] pwm: Add Loongson PWM controller support 2024-12-10 12:37 ` [PATCH v8 2/2] pwm: Add Loongson PWM controller support Binbin Zhou @ 2025-02-10 18:26 ` Uwe Kleine-König 2025-02-11 8:02 ` Binbin Zhou 0 siblings, 1 reply; 7+ messages in thread From: Uwe Kleine-König @ 2025-02-10 18:26 UTC (permalink / raw) To: Binbin Zhou Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Juxin Gao, Huacai Chen, linux-pwm, devicetree, Xuerui Wang, loongarch [-- Attachment #1: Type: text/plain, Size: 2190 bytes --] Hello Binbin, On Tue, Dec 10, 2024 at 08:37:06PM +0800, Binbin Zhou wrote: > +static int pwm_loongson_probe(struct platform_device *pdev) > +{ > + int ret; > + struct pwm_chip *chip; > + struct pwm_loongson_ddata *ddata; > + struct device *dev = &pdev->dev; > + > + chip = devm_pwmchip_alloc(dev, 1, sizeof(*ddata)); > + if (IS_ERR(chip)) > + return PTR_ERR(chip); > + ddata = to_pwm_loongson_ddata(chip); > + > + ddata->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(ddata->base)) > + return PTR_ERR(ddata->base); > + > + ddata->clk = devm_clk_get_optional_enabled(dev, NULL); > + if (IS_ERR(ddata->clk)) > + return dev_err_probe(dev, PTR_ERR(ddata->clk), > + "failed to get pwm clock\n"); > + if (ddata->clk) { > + ret = devm_clk_rate_exclusive_get(dev, ddata->clk); > + if (ret) > + return ret; Error message please. Also please make all errors start with a capital letter. > + ddata->clk_rate = clk_get_rate(ddata->clk); > + } else { > + ddata->clk_rate = LOONGSON_PWM_FREQ_DEFAULT; > + } > + > + /* Explicitly initialize the CTRL register */ > + pwm_loongson_writel(ddata, 0, LOONGSON_PWM_REG_CTRL); This disables all outputs, right? Ideally the driver takes over running channels. Consider the bootloader initialized a display with a splash screen. Disabling the PWM might disable the backlight of the display which hurts the visual experience. > + chip->ops = &pwm_loongson_ops; > + chip->atomic = true; > + dev_set_drvdata(dev, chip); > + > + ret = devm_pwmchip_add(dev, chip); > + if (ret < 0) > + return dev_err_probe(dev, ret, "failed to add PWM chip\n"); > + > + return 0; > +} > + > +static int pwm_loongson_suspend(struct device *dev) > +{ > + struct pwm_chip *chip = dev_get_drvdata(dev); > + struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); > + > + ddata->lss.ctrl = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); > + ddata->lss.duty = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_DUTY); > + ddata->lss.period = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_PERIOD); > + > + clk_disable_unprepare(ddata->clk); > + > + return 0; Is this needed assuming that before suspend the consumer stopped the PWM? Best regards Uwe [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v8 2/2] pwm: Add Loongson PWM controller support 2025-02-10 18:26 ` Uwe Kleine-König @ 2025-02-11 8:02 ` Binbin Zhou 2025-02-11 17:36 ` Uwe Kleine-König 0 siblings, 1 reply; 7+ messages in thread From: Binbin Zhou @ 2025-02-11 8:02 UTC (permalink / raw) To: Uwe Kleine-König Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Juxin Gao, Huacai Chen, linux-pwm, devicetree, Xuerui Wang, loongarch Hi Uwe: Thanks for your review. On Tue, Feb 11, 2025 at 12:26 AM Uwe Kleine-König <ukleinek@kernel.org> wrote: > > Hello Binbin, > > On Tue, Dec 10, 2024 at 08:37:06PM +0800, Binbin Zhou wrote: > > +static int pwm_loongson_probe(struct platform_device *pdev) > > +{ > > + int ret; > > + struct pwm_chip *chip; > > + struct pwm_loongson_ddata *ddata; > > + struct device *dev = &pdev->dev; > > + > > + chip = devm_pwmchip_alloc(dev, 1, sizeof(*ddata)); > > + if (IS_ERR(chip)) > > + return PTR_ERR(chip); > > + ddata = to_pwm_loongson_ddata(chip); > > + > > + ddata->base = devm_platform_ioremap_resource(pdev, 0); > > + if (IS_ERR(ddata->base)) > > + return PTR_ERR(ddata->base); > > + > > + ddata->clk = devm_clk_get_optional_enabled(dev, NULL); > > + if (IS_ERR(ddata->clk)) > > + return dev_err_probe(dev, PTR_ERR(ddata->clk), > > + "failed to get pwm clock\n"); > > + if (ddata->clk) { > > + ret = devm_clk_rate_exclusive_get(dev, ddata->clk); > > + if (ret) > > + return ret; > > Error message please. Also please make all errors start with a capital > letter. Ok, I will do it. > > > + ddata->clk_rate = clk_get_rate(ddata->clk); > > + } else { > > + ddata->clk_rate = LOONGSON_PWM_FREQ_DEFAULT; > > + } > > + > > + /* Explicitly initialize the CTRL register */ > > + pwm_loongson_writel(ddata, 0, LOONGSON_PWM_REG_CTRL); > > This disables all outputs, right? Ideally the driver takes over running > channels. Consider the bootloader initialized a display with a splash > screen. Disabling the PWM might disable the backlight of the display > which hurts the visual experience. Indeed, there may be similar problems. I don't have similar hardware at the moment, and just in case, I think it would be more appropriate to follow the pwm settings of the bootloader. I'll try to drop it in the next version. > > > + chip->ops = &pwm_loongson_ops; > > + chip->atomic = true; > > + dev_set_drvdata(dev, chip); > > + > > + ret = devm_pwmchip_add(dev, chip); > > + if (ret < 0) > > + return dev_err_probe(dev, ret, "failed to add PWM chip\n"); > > + > > + return 0; > > +} > > + > > +static int pwm_loongson_suspend(struct device *dev) > > +{ > > + struct pwm_chip *chip = dev_get_drvdata(dev); > > + struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); > > + > > + ddata->lss.ctrl = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); > > + ddata->lss.duty = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_DUTY); > > + ddata->lss.period = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_PERIOD); > > + > > + clk_disable_unprepare(ddata->clk); > > + > > + return 0; > > Is this needed assuming that before suspend the consumer stopped the > PWM? Actually, I don't quite understand the problem you're pointing out. It seems to me that the register and clk operations are required regardless of the state of the pwm. At least from the experimental results, the logic is now as expected. Of course, I may be missing some critical information. > > Best regards > Uwe > -- Thanks. Binbin ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v8 2/2] pwm: Add Loongson PWM controller support 2025-02-11 8:02 ` Binbin Zhou @ 2025-02-11 17:36 ` Uwe Kleine-König 2025-02-12 7:51 ` Binbin Zhou 0 siblings, 1 reply; 7+ messages in thread From: Uwe Kleine-König @ 2025-02-11 17:36 UTC (permalink / raw) To: Binbin Zhou Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Juxin Gao, Huacai Chen, linux-pwm, devicetree, Xuerui Wang, loongarch [-- Attachment #1: Type: text/plain, Size: 1633 bytes --] Hello, On Tue, Feb 11, 2025 at 02:02:03PM +0600, Binbin Zhou wrote: > On Tue, Feb 11, 2025 at 12:26 AM Uwe Kleine-König <ukleinek@kernel.org> wrote: > > On Tue, Dec 10, 2024 at 08:37:06PM +0800, Binbin Zhou wrote: > > > +static int pwm_loongson_suspend(struct device *dev) > > > +{ > > > + struct pwm_chip *chip = dev_get_drvdata(dev); > > > + struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); > > > + > > > + ddata->lss.ctrl = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); > > > + ddata->lss.duty = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_DUTY); > > > + ddata->lss.period = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_PERIOD); > > > + > > > + clk_disable_unprepare(ddata->clk); > > > + > > > + return 0; > > > > Is this needed assuming that before suspend the consumer stopped the > > PWM? > > Actually, I don't quite understand the problem you're pointing out. It > seems to me that the register and clk operations are required > regardless of the state of the pwm. > At least from the experimental results, the logic is now as expected. > Of course, I may be missing some critical information. When a PWM goes into suspend it's expected that its consumer already disabled it. Until I come around to do that properly in the core for all drivers, I think the right approach in a driver is: for (i = 0; i < chip->npwm; ++i) { if (chip->pwms[i].state.enabled) return -EBUSY; } and if you then know that all PWMs are disabled, maybe you don't need to store all the registers you did in pwm_loongson_suspend()? Best regards Uwe [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v8 2/2] pwm: Add Loongson PWM controller support 2025-02-11 17:36 ` Uwe Kleine-König @ 2025-02-12 7:51 ` Binbin Zhou 0 siblings, 0 replies; 7+ messages in thread From: Binbin Zhou @ 2025-02-12 7:51 UTC (permalink / raw) To: Uwe Kleine-König Cc: Binbin Zhou, Huacai Chen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Juxin Gao, Huacai Chen, linux-pwm, devicetree, Xuerui Wang, loongarch Hi Uwe: On Tue, Feb 11, 2025 at 11:36 PM Uwe Kleine-König <ukleinek@kernel.org> wrote: > > Hello, > > On Tue, Feb 11, 2025 at 02:02:03PM +0600, Binbin Zhou wrote: > > On Tue, Feb 11, 2025 at 12:26 AM Uwe Kleine-König <ukleinek@kernel.org> wrote: > > > On Tue, Dec 10, 2024 at 08:37:06PM +0800, Binbin Zhou wrote: > > > > +static int pwm_loongson_suspend(struct device *dev) > > > > +{ > > > > + struct pwm_chip *chip = dev_get_drvdata(dev); > > > > + struct pwm_loongson_ddata *ddata = to_pwm_loongson_ddata(chip); > > > > + > > > > + ddata->lss.ctrl = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_CTRL); > > > > + ddata->lss.duty = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_DUTY); > > > > + ddata->lss.period = pwm_loongson_readl(ddata, LOONGSON_PWM_REG_PERIOD); > > > > + > > > > + clk_disable_unprepare(ddata->clk); > > > > + > > > > + return 0; > > > > > > Is this needed assuming that before suspend the consumer stopped the > > > PWM? > > > > Actually, I don't quite understand the problem you're pointing out. It > > seems to me that the register and clk operations are required > > regardless of the state of the pwm. > > At least from the experimental results, the logic is now as expected. > > Of course, I may be missing some critical information. > > When a PWM goes into suspend it's expected that its consumer already > disabled it. > > Until I come around to do that properly in the core for all drivers, I > think the right approach in a driver is: > > for (i = 0; i < chip->npwm; ++i) { > if (chip->pwms[i].state.enabled) > return -EBUSY; > } OK, I will add the approach into pwm_loongson_suspend(). Since our pwm is single channel, it can be changed to: + struct pwm_device *pwm = &chip->pwms[0]; + + if (pwm->state.enabled) + return -EBUSY; > > and if you then know that all PWMs are disabled, maybe you don't need to > store all the registers you did in pwm_loongson_suspend()? > > Best regards > Uwe -- Thanks. Binbin ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-02-12 7:51 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-12-10 12:37 [PATCH v8 0/2] pwm: Introduce pwm driver for the Loongson family chips Binbin Zhou 2024-12-10 12:37 ` [PATCH v8 1/2] dt-bindings: pwm: Add Loongson PWM controller Binbin Zhou 2024-12-10 12:37 ` [PATCH v8 2/2] pwm: Add Loongson PWM controller support Binbin Zhou 2025-02-10 18:26 ` Uwe Kleine-König 2025-02-11 8:02 ` Binbin Zhou 2025-02-11 17:36 ` Uwe Kleine-König 2025-02-12 7:51 ` Binbin Zhou
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