From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from pegase2.c-s.fr (pegase2.c-s.fr [93.17.235.10]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 001DF2D7D42; Mon, 18 Aug 2025 09:20:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=93.17.235.10 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755508851; cv=none; b=LWuAXsaaVrG8s5Ev329YjA0UQPsDu6XBOpVESZpQ1yZ1coS8qp1se6WEZv1wzFE4VrfojGND2Qbv31sm7zZ4zgIrk0lCURnqiBqcPmprq7eADmBk3SLXCE+/QnkNpYZ26/olc2S5+483kMbeswKB+Nm9Scn1Ad4FbJPw3KeiE7s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755508851; c=relaxed/simple; bh=0zMxvMtVDYI3C0qUdfZ4EOBxyOcB0ghTKA2N/7FYUng=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=JTGO6j9jvE+ICCZMw2MSSSVO6CmGf9dyJm3cy7DkAcoVH3VUZNJoP33hjeAGn6BeWWFSeoBAr6wwUqrBusWJJ15SrU5cwYFeO/stNWwmm6N2fx0kBmm1szRMgnxrqgOUFR9C+xuyMSKHfSE9ZRgq2nae/++fhkNoKl0xrt/EfXk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu; spf=pass smtp.mailfrom=csgroup.eu; arc=none smtp.client-ip=93.17.235.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=csgroup.eu Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=csgroup.eu Received: from localhost (mailhub4.si.c-s.fr [172.26.127.67]) by localhost (Postfix) with ESMTP id 4c55sY4xgJz9sWj; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from pegase2.c-s.fr ([172.26.127.65]) by localhost (pegase2.c-s.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TKGrlbOf_Qrh; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) Received: from messagerie.si.c-s.fr (messagerie.si.c-s.fr [192.168.25.192]) by pegase2.c-s.fr (Postfix) with ESMTP id 4c55sY45ysz9sWh; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 767258B765; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) X-Virus-Scanned: amavisd-new at c-s.fr Received: from messagerie.si.c-s.fr ([127.0.0.1]) by localhost (messagerie.si.c-s.fr [127.0.0.1]) (amavisd-new, port 10023) with ESMTP id MrqQklRryYxw; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) Received: from PO20335.idsi0.si.c-s.fr (unknown [10.25.207.160]) by messagerie.si.c-s.fr (Postfix) with ESMTP id 4E0F48B763; Mon, 18 Aug 2025 10:46:09 +0200 (CEST) From: Christophe Leroy To: Qiang Zhao , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Christophe Leroy , linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v2 0/5] Add support of IRQs to QUICC ENGINE GPIOs Date: Mon, 18 Aug 2025 10:45:53 +0200 Message-ID: X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755506759; l=1744; i=christophe.leroy@csgroup.eu; s=20211009; h=from:subject:message-id; bh=0zMxvMtVDYI3C0qUdfZ4EOBxyOcB0ghTKA2N/7FYUng=; b=tL7X0n2yGtytrRK48Qz0+3gJn380KbagfKlBBXXWBcvgq0NLI5zZcEzp21zG1+Ed5JQcE+B8J 79JqZWIKUf0B1fKRLDVzvS9O6zqRvtkttEaDYwlmtNYrscdF30FdLSz X-Developer-Key: i=christophe.leroy@csgroup.eu; a=ed25519; pk=HIzTzUj91asvincQGOFx6+ZF5AoUuP9GdOtQChs7Mm0= Content-Transfer-Encoding: 8bit The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for those IRQs then add IRQs capability to the QUICC ENGINE GPIOs. The number of GPIOs for which interrupts are supported depends on the microcontroller: - mpc8323 has 10 GPIOS supporting interrupts - mpc8360 has 28 GPIOS supporting interrupts - mpc8568 has 18 GPIOS supporting interrupts Changes in v2: - Fixed warning on PPC64 build (Patch 1) - Using devm_kzalloc() instead of kzalloc (Patch 2) - Stop using of-mm-gpiochip (New patch 3) - Added fsl,qe-gpio-irq-mask propertie in DT binding doc (Patch 4) - Fixed problems reported by 'make dt_binding_check' (Patch 5) Christophe Leroy (5): soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports soc: fsl: qe: Change GPIO driver to a proper platform driver soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver soc: fsl: qe: Add support of IRQ in QE GPIO dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports .../soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml | 58 +++++++ .../bindings/soc/fsl/cpm_qe/qe/par_io.txt | 19 +++ arch/powerpc/platforms/Kconfig | 1 - drivers/soc/fsl/qe/Makefile | 2 +- drivers/soc/fsl/qe/gpio.c | 145 +++++++++------- drivers/soc/fsl/qe/qe_ports_ic.c | 156 ++++++++++++++++++ 6 files changed, 322 insertions(+), 59 deletions(-) create mode 100644 Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,qe-ports-ic.yaml create mode 100644 drivers/soc/fsl/qe/qe_ports_ic.c -- 2.49.0