* [PATCH v3 1/7] dt-bindings: pci: Add Sophgo SG2042 PCIe host
2025-09-12 2:35 [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC Chen Wang
@ 2025-09-12 2:35 ` Chen Wang
2025-09-12 2:36 ` [PATCH v3 2/7] PCI: cadence: Check pcie-ops before using it Chen Wang
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Chen Wang @ 2025-09-12 2:35 UTC (permalink / raw)
To: kwilczynski, u.kleine-koenig, aou, alex, arnd, bwawrzyn, bhelgaas,
unicorn_wang, conor+dt, 18255117159, inochiama, kishon, krzk+dt,
lpieralisi, mani, palmer, paul.walmsley, robh, s-vadapalli, tglx,
thomas.richard, sycamoremoon376, devicetree, linux-kernel,
linux-pci, linux-riscv, sophgo, rabenda.cn, chao.wei,
xiaoguang.xing, fengchun.li, jeffbai
From: Chen Wang <unicorn_wang@outlook.com>
Add binding for Sophgo SG2042 PCIe host controller.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
.../bindings/pci/sophgo,sg2042-pcie-host.yaml | 64 +++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
new file mode 100644
index 000000000000..f8b7ca57fff1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper)
+
+description:
+ Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core.
+
+maintainers:
+ - Chen Wang <unicorn_wang@outlook.com>
+
+properties:
+ compatible:
+ const: sophgo,sg2042-pcie-host
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: reg
+ - const: cfg
+
+ vendor-id:
+ const: 0x1f1c
+
+ device-id:
+ const: 0x2042
+
+ msi-parent: true
+
+allOf:
+ - $ref: cdns-pcie-host.yaml#
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pcie@62000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x62000000 0x00800000>,
+ <0x48000000 0x00001000>;
+ reg-names = "reg", "cfg";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
+ <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
+ bus-range = <0x00 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v3 2/7] PCI: cadence: Check pcie-ops before using it
2025-09-12 2:35 [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC Chen Wang
2025-09-12 2:35 ` [PATCH v3 1/7] dt-bindings: pci: Add Sophgo SG2042 PCIe host Chen Wang
@ 2025-09-12 2:36 ` Chen Wang
2025-09-12 2:36 ` [PATCH v3 3/7] PCI: sg2042: Add Sophgo SG2042 PCIe driver Chen Wang
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Chen Wang @ 2025-09-12 2:36 UTC (permalink / raw)
To: kwilczynski, u.kleine-koenig, aou, alex, arnd, bwawrzyn, bhelgaas,
unicorn_wang, conor+dt, 18255117159, inochiama, kishon, krzk+dt,
lpieralisi, mani, palmer, paul.walmsley, robh, s-vadapalli, tglx,
thomas.richard, sycamoremoon376, devicetree, linux-kernel,
linux-pci, linux-riscv, sophgo, rabenda.cn, chao.wei,
xiaoguang.xing, fengchun.li, jeffbai
From: Chen Wang <unicorn_wang@outlook.com>
ops of struct cdns_pcie may be NULL, direct use
will result in a null pointer error.
Add checking of pcie->ops before using it for new
driver that may not supply pcie->ops.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
drivers/pci/controller/cadence/pcie-cadence-host.c | 2 +-
drivers/pci/controller/cadence/pcie-cadence.c | 4 ++--
drivers/pci/controller/cadence/pcie-cadence.h | 6 +++---
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 59a4631de79f..fffd63d6665e 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -531,7 +531,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
- if (pcie->ops->cpu_addr_fixup)
+ if (pcie->ops && pcie->ops->cpu_addr_fixup)
cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |
diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
index 70a19573440e..61806bbd8aa3 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.c
+++ b/drivers/pci/controller/cadence/pcie-cadence.c
@@ -92,7 +92,7 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
/* Set the CPU address */
- if (pcie->ops->cpu_addr_fixup)
+ if (pcie->ops && pcie->ops->cpu_addr_fixup)
cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
@@ -123,7 +123,7 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
}
/* Set the CPU address */
- if (pcie->ops->cpu_addr_fixup)
+ if (pcie->ops && pcie->ops->cpu_addr_fixup)
cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) |
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 1d81c4bf6c6d..2f07ba661bda 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -468,7 +468,7 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)
static inline int cdns_pcie_start_link(struct cdns_pcie *pcie)
{
- if (pcie->ops->start_link)
+ if (pcie->ops && pcie->ops->start_link)
return pcie->ops->start_link(pcie);
return 0;
@@ -476,13 +476,13 @@ static inline int cdns_pcie_start_link(struct cdns_pcie *pcie)
static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie)
{
- if (pcie->ops->stop_link)
+ if (pcie->ops && pcie->ops->stop_link)
pcie->ops->stop_link(pcie);
}
static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie)
{
- if (pcie->ops->link_up)
+ if (pcie->ops && pcie->ops->link_up)
return pcie->ops->link_up(pcie);
return true;
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v3 3/7] PCI: sg2042: Add Sophgo SG2042 PCIe driver
2025-09-12 2:35 [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC Chen Wang
2025-09-12 2:35 ` [PATCH v3 1/7] dt-bindings: pci: Add Sophgo SG2042 PCIe host Chen Wang
2025-09-12 2:36 ` [PATCH v3 2/7] PCI: cadence: Check pcie-ops before using it Chen Wang
@ 2025-09-12 2:36 ` Chen Wang
2025-09-12 2:36 ` [PATCH v3 4/7] riscv: sophgo: dts: add PCIe controllers for SG2042 Chen Wang
` (5 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Chen Wang @ 2025-09-12 2:36 UTC (permalink / raw)
To: kwilczynski, u.kleine-koenig, aou, alex, arnd, bwawrzyn, bhelgaas,
unicorn_wang, conor+dt, 18255117159, inochiama, kishon, krzk+dt,
lpieralisi, mani, palmer, paul.walmsley, robh, s-vadapalli, tglx,
thomas.richard, sycamoremoon376, devicetree, linux-kernel,
linux-pci, linux-riscv, sophgo, rabenda.cn, chao.wei,
xiaoguang.xing, fengchun.li, jeffbai
From: Chen Wang <unicorn_wang@outlook.com>
Add support for PCIe controller in SG2042 SoC. The controller
uses the Cadence PCIe core programmed by pcie-cadence*.c. The
PCIe controller will work in host mode only, supporting data
rate (16 GT/s) and lanes (x16 or x8).
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
drivers/pci/controller/cadence/Kconfig | 10 ++
drivers/pci/controller/cadence/Makefile | 1 +
drivers/pci/controller/cadence/pcie-sg2042.c | 138 +++++++++++++++++++
3 files changed, 149 insertions(+)
create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c
diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
index 666e16b6367f..02a639e55fd8 100644
--- a/drivers/pci/controller/cadence/Kconfig
+++ b/drivers/pci/controller/cadence/Kconfig
@@ -42,6 +42,15 @@ config PCIE_CADENCE_PLAT_EP
endpoint mode. This PCIe controller may be embedded into many
different vendors SoCs.
+config PCIE_SG2042_HOST
+ tristate "Sophgo SG2042 PCIe controller (host mode)"
+ depends on OF && (ARCH_SOPHGO || COMPILE_TEST)
+ select PCIE_CADENCE_HOST
+ help
+ Say Y here if you want to support the Sophgo SG2042 PCIe platform
+ controller in host mode. Sophgo SG2042 PCIe controller uses Cadence
+ PCIe core.
+
config PCI_J721E
tristate
select PCIE_CADENCE_HOST if PCI_J721E_HOST != n
@@ -67,4 +76,5 @@ config PCI_J721E_EP
Say Y here if you want to support the TI J721E PCIe platform
controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe
core.
+
endmenu
diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile
index 9bac5fb2f13d..5e23f8539ecc 100644
--- a/drivers/pci/controller/cadence/Makefile
+++ b/drivers/pci/controller/cadence/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
obj-$(CONFIG_PCI_J721E) += pci-j721e.o
+obj-$(CONFIG_PCIE_SG2042_HOST) += pcie-sg2042.o
diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c
new file mode 100644
index 000000000000..db91c37790b7
--- /dev/null
+++ b/drivers/pci/controller/cadence/pcie-sg2042.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC
+ *
+ * Copyright (C) 2025 Sophgo Technology Inc.
+ * Copyright (C) 2025 Chen Wang <unicorn_wang@outlook.com>
+ */
+
+#include <linux/mod_devicetable.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include "pcie-cadence.h"
+
+/*
+ * SG2042 only supports 4-byte aligned access, so for the rootbus (i.e. to
+ * read/write the Root Port itself, read32/write32 is required. For
+ * non-rootbus (i.e. to read/write the PCIe peripheral registers, supports
+ * 1/2/4 byte aligned access, so directly using read/write should be fine.
+ */
+
+static struct pci_ops sg2042_pcie_root_ops = {
+ .map_bus = cdns_pci_map_bus,
+ .read = pci_generic_config_read32,
+ .write = pci_generic_config_write32,
+};
+
+static struct pci_ops sg2042_pcie_child_ops = {
+ .map_bus = cdns_pci_map_bus,
+ .read = pci_generic_config_read,
+ .write = pci_generic_config_write,
+};
+
+static int sg2042_pcie_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pci_host_bridge *bridge;
+ struct cdns_pcie *pcie;
+ struct cdns_pcie_rc *rc;
+ int ret;
+
+ bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
+ if (!bridge) {
+ dev_err_probe(dev, -ENOMEM, "Failed to alloc host bridge!\n");
+ return -ENOMEM;
+ }
+
+ bridge->ops = &sg2042_pcie_root_ops;
+ bridge->child_ops = &sg2042_pcie_child_ops;
+
+ rc = pci_host_bridge_priv(bridge);
+ pcie = &rc->pcie;
+ pcie->dev = dev;
+
+ platform_set_drvdata(pdev, pcie);
+
+ pm_runtime_set_active(dev);
+ pm_runtime_no_callbacks(dev);
+ devm_pm_runtime_enable(dev);
+
+ ret = cdns_pcie_init_phy(dev, pcie);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to init phy!\n");
+ return ret;
+ }
+
+ ret = cdns_pcie_host_setup(rc);
+ if (ret) {
+ dev_err_probe(dev, ret, "Failed to setup host!\n");
+ cdns_pcie_disable_phy(pcie);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void sg2042_pcie_remove(struct platform_device *pdev)
+{
+ struct cdns_pcie *pcie = platform_get_drvdata(pdev);
+ struct device *dev = &pdev->dev;
+ struct cdns_pcie_rc *rc;
+
+ rc = container_of(pcie, struct cdns_pcie_rc, pcie);
+ cdns_pcie_host_disable(rc);
+
+ cdns_pcie_disable_phy(pcie);
+
+ pm_runtime_disable(dev);
+}
+
+static int sg2042_pcie_suspend_noirq(struct device *dev)
+{
+ struct cdns_pcie *pcie = dev_get_drvdata(dev);
+
+ cdns_pcie_disable_phy(pcie);
+
+ return 0;
+}
+
+static int sg2042_pcie_resume_noirq(struct device *dev)
+{
+ struct cdns_pcie *pcie = dev_get_drvdata(dev);
+ int ret;
+
+ ret = cdns_pcie_enable_phy(pcie);
+ if (ret) {
+ dev_err(dev, "failed to enable PHY\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static DEFINE_NOIRQ_DEV_PM_OPS(sg2042_pcie_pm_ops,
+ sg2042_pcie_suspend_noirq,
+ sg2042_pcie_resume_noirq);
+
+static const struct of_device_id sg2042_pcie_of_match[] = {
+ { .compatible = "sophgo,sg2042-pcie-host" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, sg2042_pcie_of_match);
+
+static struct platform_driver sg2042_pcie_driver = {
+ .driver = {
+ .name = "sg2042-pcie",
+ .of_match_table = sg2042_pcie_of_match,
+ .pm = pm_sleep_ptr(&sg2042_pcie_pm_ops),
+ },
+ .probe = sg2042_pcie_probe,
+ .remove = sg2042_pcie_remove,
+};
+module_platform_driver(sg2042_pcie_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("PCIe controller driver for SG2042 SoCs");
+MODULE_AUTHOR("Chen Wang <unicorn_wang@outlook.com>");
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v3 4/7] riscv: sophgo: dts: add PCIe controllers for SG2042
2025-09-12 2:35 [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC Chen Wang
` (2 preceding siblings ...)
2025-09-12 2:36 ` [PATCH v3 3/7] PCI: sg2042: Add Sophgo SG2042 PCIe driver Chen Wang
@ 2025-09-12 2:36 ` Chen Wang
2025-09-20 7:42 ` Manivannan Sadhasivam
2025-09-12 2:37 ` [PATCH v3 5/7] riscv: sophgo: dts: enable PCIe for PioneerBox Chen Wang
` (4 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Chen Wang @ 2025-09-12 2:36 UTC (permalink / raw)
To: kwilczynski, u.kleine-koenig, aou, alex, arnd, bwawrzyn, bhelgaas,
unicorn_wang, conor+dt, 18255117159, inochiama, kishon, krzk+dt,
lpieralisi, mani, palmer, paul.walmsley, robh, s-vadapalli, tglx,
thomas.richard, sycamoremoon376, devicetree, linux-kernel,
linux-pci, linux-riscv, sophgo, rabenda.cn, chao.wei,
xiaoguang.xing, fengchun.li, jeffbai
From: Chen Wang <unicorn_wang@outlook.com>
Add PCIe controller nodes in DTS for Sophgo SG2042.
Default they are disabled.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index b3e4d3c18fdc..b521f674283e 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -220,6 +220,94 @@ clkgen: clock-controller@7030012000 {
#clock-cells = <1>;
};
+ pcie_rc0: pcie@7060000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60000000 0x0 0x00800000>,
+ <0x40 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc1: pcie@7060800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x60800000 0x0 0x00800000>,
+ <0x44 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
+ <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc2: pcie@7062000000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62000000 0x0 0x00800000>,
+ <0x48 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>,
+ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
+ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
+ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
+ pcie_rc3: pcie@7062800000 {
+ compatible = "sophgo,sg2042-pcie-host";
+ device_type = "pci";
+ reg = <0x70 0x62800000 0x0 0x00800000>,
+ <0x4c 0x00000000 0x0 0x00001000>;
+ reg-names = "reg", "cfg";
+ linux,pci-domain = <3>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>,
+ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
+ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
+ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
+ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
+ bus-range = <0x0 0xff>;
+ vendor-id = <0x1f1c>;
+ device-id = <0x2042>;
+ cdns,no-bar-match-nbits = <48>;
+ msi-parent = <&msi>;
+ status = "disabled";
+ };
+
clint_mswi: interrupt-controller@7094000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v3 4/7] riscv: sophgo: dts: add PCIe controllers for SG2042
2025-09-12 2:36 ` [PATCH v3 4/7] riscv: sophgo: dts: add PCIe controllers for SG2042 Chen Wang
@ 2025-09-20 7:42 ` Manivannan Sadhasivam
2025-09-28 23:53 ` Chen Wang
0 siblings, 1 reply; 12+ messages in thread
From: Manivannan Sadhasivam @ 2025-09-20 7:42 UTC (permalink / raw)
To: Chen Wang
Cc: kwilczynski, u.kleine-koenig, aou, alex, arnd, bwawrzyn, bhelgaas,
unicorn_wang, conor+dt, 18255117159, inochiama, kishon, krzk+dt,
lpieralisi, palmer, paul.walmsley, robh, s-vadapalli, tglx,
thomas.richard, sycamoremoon376, devicetree, linux-kernel,
linux-pci, linux-riscv, sophgo, rabenda.cn, chao.wei,
xiaoguang.xing, fengchun.li, jeffbai
On Fri, Sep 12, 2025 at 10:36:50AM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
>
> Add PCIe controller nodes in DTS for Sophgo SG2042.
> Default they are disabled.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
> ---
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index b3e4d3c18fdc..b521f674283e 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -220,6 +220,94 @@ clkgen: clock-controller@7030012000 {
> #clock-cells = <1>;
> };
>
> + pcie_rc0: pcie@7060000000 {
> + compatible = "sophgo,sg2042-pcie-host";
> + device_type = "pci";
> + reg = <0x70 0x60000000 0x0 0x00800000>,
> + <0x40 0x00000000 0x0 0x00001000>;
> + reg-names = "reg", "cfg";
> + linux,pci-domain = <0>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>,
PCI address of the I/O port starts from 0. So this should be:
<0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
Same comment for other nodes.
With this fixed,
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
- Mani
> + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
> + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
> + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
> + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
> + bus-range = <0x0 0xff>;
> + vendor-id = <0x1f1c>;
> + device-id = <0x2042>;
> + cdns,no-bar-match-nbits = <48>;
> + msi-parent = <&msi>;
> + status = "disabled";
> + };
> +
> + pcie_rc1: pcie@7060800000 {
> + compatible = "sophgo,sg2042-pcie-host";
> + device_type = "pci";
> + reg = <0x70 0x60800000 0x0 0x00800000>,
> + <0x44 0x00000000 0x0 0x00001000>;
> + reg-names = "reg", "cfg";
> + linux,pci-domain = <1>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>,
> + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
> + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
> + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
> + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
> + bus-range = <0x0 0xff>;
> + vendor-id = <0x1f1c>;
> + device-id = <0x2042>;
> + cdns,no-bar-match-nbits = <48>;
> + msi-parent = <&msi>;
> + status = "disabled";
> + };
> +
> + pcie_rc2: pcie@7062000000 {
> + compatible = "sophgo,sg2042-pcie-host";
> + device_type = "pci";
> + reg = <0x70 0x62000000 0x0 0x00800000>,
> + <0x48 0x00000000 0x0 0x00001000>;
> + reg-names = "reg", "cfg";
> + linux,pci-domain = <2>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>,
> + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
> + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
> + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
> + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
> + bus-range = <0x0 0xff>;
> + vendor-id = <0x1f1c>;
> + device-id = <0x2042>;
> + cdns,no-bar-match-nbits = <48>;
> + msi-parent = <&msi>;
> + status = "disabled";
> + };
> +
> + pcie_rc3: pcie@7062800000 {
> + compatible = "sophgo,sg2042-pcie-host";
> + device_type = "pci";
> + reg = <0x70 0x62800000 0x0 0x00800000>,
> + <0x4c 0x00000000 0x0 0x00001000>;
> + reg-names = "reg", "cfg";
> + linux,pci-domain = <3>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>,
> + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
> + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
> + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
> + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
> + bus-range = <0x0 0xff>;
> + vendor-id = <0x1f1c>;
> + device-id = <0x2042>;
> + cdns,no-bar-match-nbits = <48>;
> + msi-parent = <&msi>;
> + status = "disabled";
> + };
> +
> clint_mswi: interrupt-controller@7094000000 {
> compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
> reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 4/7] riscv: sophgo: dts: add PCIe controllers for SG2042
2025-09-20 7:42 ` Manivannan Sadhasivam
@ 2025-09-28 23:53 ` Chen Wang
0 siblings, 0 replies; 12+ messages in thread
From: Chen Wang @ 2025-09-28 23:53 UTC (permalink / raw)
To: Manivannan Sadhasivam, Chen Wang
Cc: kwilczynski, u.kleine-koenig, aou, alex, arnd, bwawrzyn, bhelgaas,
conor+dt, 18255117159, inochiama, kishon, krzk+dt, lpieralisi,
palmer, paul.walmsley, robh, s-vadapalli, tglx, thomas.richard,
sycamoremoon376, devicetree, linux-kernel, linux-pci, linux-riscv,
sophgo, rabenda.cn, chao.wei, xiaoguang.xing, fengchun.li,
jeffbai
On 9/20/2025 3:42 PM, Manivannan Sadhasivam wrote:
> On Fri, Sep 12, 2025 at 10:36:50AM +0800, Chen Wang wrote:
>> From: Chen Wang <unicorn_wang@outlook.com>
>>
>> Add PCIe controller nodes in DTS for Sophgo SG2042.
>> Default they are disabled.
>>
>> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
>> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
>> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
>> ---
>> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 ++++++++++++++++++++++++++
>> 1 file changed, 88 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
>> index b3e4d3c18fdc..b521f674283e 100644
>> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
>> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
>> @@ -220,6 +220,94 @@ clkgen: clock-controller@7030012000 {
>> #clock-cells = <1>;
>> };
>>
>> + pcie_rc0: pcie@7060000000 {
>> + compatible = "sophgo,sg2042-pcie-host";
>> + device_type = "pci";
>> + reg = <0x70 0x60000000 0x0 0x00800000>,
>> + <0x40 0x00000000 0x0 0x00001000>;
>> + reg-names = "reg", "cfg";
>> + linux,pci-domain = <0>;
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> + ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>,
> PCI address of the I/O port starts from 0. So this should be:
>
> <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
>
> Same comment for other nodes.
>
> With this fixed,
>
> Acked-by: Manivannan Sadhasivam <mani@kernel.org>
>
> - Mani
Thanks, I will fix this in next version.
[......]
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 5/7] riscv: sophgo: dts: enable PCIe for PioneerBox
2025-09-12 2:35 [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC Chen Wang
` (3 preceding siblings ...)
2025-09-12 2:36 ` [PATCH v3 4/7] riscv: sophgo: dts: add PCIe controllers for SG2042 Chen Wang
@ 2025-09-12 2:37 ` Chen Wang
2025-09-12 2:37 ` [PATCH v3 6/7] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X Chen Wang
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Chen Wang @ 2025-09-12 2:37 UTC (permalink / raw)
To: kwilczynski, u.kleine-koenig, aou, alex, arnd, bwawrzyn, bhelgaas,
unicorn_wang, conor+dt, 18255117159, inochiama, kishon, krzk+dt,
lpieralisi, mani, palmer, paul.walmsley, robh, s-vadapalli, tglx,
thomas.richard, sycamoremoon376, devicetree, linux-kernel,
linux-pci, linux-riscv, sophgo, rabenda.cn, chao.wei,
xiaoguang.xing, fengchun.li, jeffbai
From: Chen Wang <unicorn_wang@outlook.com>
Enable PCIe controllers for PioneerBox, which uses SG2042 SoC.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
index ef3a602172b1..c4d5f8d7d4ad 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
@@ -128,6 +128,18 @@ uart0-rx-pins {
};
};
+&pcie_rc0 {
+ status = "okay";
+};
+
+&pcie_rc2 {
+ status = "okay";
+};
+
+&pcie_rc3 {
+ status = "okay";
+};
+
&sd {
pinctrl-0 = <&sd_cfg>;
pinctrl-names = "default";
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v3 6/7] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
2025-09-12 2:35 [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC Chen Wang
` (4 preceding siblings ...)
2025-09-12 2:37 ` [PATCH v3 5/7] riscv: sophgo: dts: enable PCIe for PioneerBox Chen Wang
@ 2025-09-12 2:37 ` Chen Wang
2025-09-12 2:37 ` [PATCH v3 7/7] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0 Chen Wang
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Chen Wang @ 2025-09-12 2:37 UTC (permalink / raw)
To: kwilczynski, u.kleine-koenig, aou, alex, arnd, bwawrzyn, bhelgaas,
unicorn_wang, conor+dt, 18255117159, inochiama, kishon, krzk+dt,
lpieralisi, mani, palmer, paul.walmsley, robh, s-vadapalli, tglx,
thomas.richard, sycamoremoon376, devicetree, linux-kernel,
linux-pci, linux-riscv, sophgo, rabenda.cn, chao.wei,
xiaoguang.xing, fengchun.li, jeffbai
From: Chen Wang <unicorn_wang@outlook.com>
Enable PCIe controllers for Sophgo SG2042_EVB_V1.X board,
which uses SG2042 SoC.
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
index 3320bc1dd2c6..a186d036cf36 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts
@@ -164,6 +164,18 @@ phy0: phy@0 {
};
};
+&pcie_rc0 {
+ status = "okay";
+};
+
+&pcie_rc1 {
+ status = "okay";
+};
+
+&pcie_rc2 {
+ status = "okay";
+};
+
&pinctrl {
emmc_cfg: sdhci-emmc-cfg {
sdhci-emmc-wp-pins {
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v3 7/7] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0
2025-09-12 2:35 [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC Chen Wang
` (5 preceding siblings ...)
2025-09-12 2:37 ` [PATCH v3 6/7] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X Chen Wang
@ 2025-09-12 2:37 ` Chen Wang
2025-09-16 11:06 ` [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC Chen Wang
2025-09-19 18:24 ` (subset) " Manivannan Sadhasivam
8 siblings, 0 replies; 12+ messages in thread
From: Chen Wang @ 2025-09-12 2:37 UTC (permalink / raw)
To: kwilczynski, u.kleine-koenig, aou, alex, arnd, bwawrzyn, bhelgaas,
unicorn_wang, conor+dt, 18255117159, inochiama, kishon, krzk+dt,
lpieralisi, mani, palmer, paul.walmsley, robh, s-vadapalli, tglx,
thomas.richard, sycamoremoon376, devicetree, linux-kernel,
linux-pci, linux-riscv, sophgo, rabenda.cn, chao.wei,
xiaoguang.xing, fengchun.li, jeffbai
From: Chen Wang <unicorn_wang@outlook.com>
Enable PCIe controllers for Sophgo SG2042_EVB_V2.0 board,
which uses SG2042 SoC.
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
---
arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
index 46980e41b886..0cd0dc0f537c 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
@@ -152,6 +152,18 @@ phy0: phy@0 {
};
};
+&pcie_rc0 {
+ status = "okay";
+};
+
+&pcie_rc1 {
+ status = "okay";
+};
+
+&pcie_rc2 {
+ status = "okay";
+};
+
&pinctrl {
emmc_cfg: sdhci-emmc-cfg {
sdhci-emmc-wp-pins {
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC
2025-09-12 2:35 [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC Chen Wang
` (6 preceding siblings ...)
2025-09-12 2:37 ` [PATCH v3 7/7] riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0 Chen Wang
@ 2025-09-16 11:06 ` Chen Wang
2025-09-19 18:24 ` (subset) " Manivannan Sadhasivam
8 siblings, 0 replies; 12+ messages in thread
From: Chen Wang @ 2025-09-16 11:06 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Chen Wang, kwilczynski, u.kleine-koenig, aou, alex, arnd,
bwawrzyn, bhelgaas, conor+dt, 18255117159, inochiama, kishon,
krzk+dt, lpieralisi, mani, palmer, paul.walmsley, robh,
s-vadapalli, tglx, thomas.richard, sycamoremoon376, devicetree,
linux-kernel, linux-pci, linux-riscv, sophgo, rabenda.cn,
chao.wei, xiaoguang.xing, fengchun.li, jeffbai
Hello, Bjorn,
Is it ok for you to pick this patchset, so we can see this in next 6.18.
You can pick [1/7]~[3/7], I can handle the left dts part.
Thanks,
Chen
On 9/12/2025 10:35 AM, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
>
> Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode.
>
> This is a completely rewritten PCIe driver for SG2042. It inherits
> some previously submitted patch codes (not merged into the upstream
> mainline), but the biggest difference is that the support for
> compatibility with old 32-bit PCIe devices has been removed in this
> new version. This is because after discussing with community users,
> we felt that there was not much demand for support for old devices,
> so we made a new design based on the simplified design and practical
> needs. If someone really needs to play with old devices, we can provide
> them with some necessary hack patches in the downstream repository.
>
> Since the new design is quite different from the old code, I will
> release it as a new patch series. The old patch series can be found in
> here [old-series].
>
> Note, regarding [2/7] of this patchset, this fix is introduced because
> the pcie->ops pointer is not filled in SG2042 PCIe driver. This is not
> a must-have parameter, if we use it w/o checking will cause a null
> pointer access error during runtime.
>
> Link: https://lore.kernel.org/linux-riscv/cover.1736923025.git.unicorn_wang@outlook.com/ [old-series]
>
> Thanks,
> Chen
>
> ---
>
> Changes in v3:
>
> This patchset is based on v6.17-rc1.
>
> Fixed following issues for driver code based on feedbacks from Bjorn Helgaas,
> Mingcong Bai, thanks.
>
> - Fixed the issue when building the driver as a module. Define own pm_ops
> inside driver, don't use the ops defined in other built-in drivers.
> - Improve .remove() function to properly disable the host.
>
> Changes in v2:
>
> This patchset is based on v6.17-rc1. You can simply review or test the
> patches at the link [2].
>
> Fixed following issues based on feedbacks from Rob Herring, Manivannan Sadhasivam,
> Bjorn Helgaas, ALOK TIWARI, thanks.
>
> - Driver binding:
> - Removed vendor-id/device-id from "required" property.
> - Improve drivers code:
> - Have separated pci_ops for the root bus and child buses.
> - Make the driver tristate and as a module.
> - Change the configuration name from PCIE_SG2042 to PCIE_SG2042_HOST.
> - Removed "Fixes" tag from commit [2/7], since this is not for an existing bug fix.
> - Other code cleanups and optimizations
> - DT:
> - Add PCIe support for SG2042 EVB boards.
>
> Changes in v1:
>
> The patch series is based on v6.17-rc1. You can simply review or test the
> patches at the link [1].
>
> Link: https://lore.kernel.org/linux-riscv/cover.1756344464.git.unicorn_wang@outlook.com/ [1]
> Link: https://lore.kernel.org/linux-riscv/cover.1757467895.git.unicorn_wang@outlook.com/ [2]
>
> ---
>
> Chen Wang (7):
> dt-bindings: pci: Add Sophgo SG2042 PCIe host
> PCI: cadence: Check pcie-ops before using it
> PCI: sg2042: Add Sophgo SG2042 PCIe driver
> riscv: sophgo: dts: add PCIe controllers for SG2042
> riscv: sophgo: dts: enable PCIe for PioneerBox
> riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X
> riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0
>
> .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 64 ++++++++
> arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 ++
> arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++
> .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 +++++++++++
> drivers/pci/controller/cadence/Kconfig | 10 ++
> drivers/pci/controller/cadence/Makefile | 1 +
> .../controller/cadence/pcie-cadence-host.c | 2 +-
> drivers/pci/controller/cadence/pcie-cadence.c | 4 +-
> drivers/pci/controller/cadence/pcie-cadence.h | 6 +-
> drivers/pci/controller/cadence/pcie-sg2042.c | 138 ++++++++++++++++++
> 11 files changed, 343 insertions(+), 6 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
> create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c
>
>
> base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: (subset) [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC
2025-09-12 2:35 [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC Chen Wang
` (7 preceding siblings ...)
2025-09-16 11:06 ` [PATCH v3 0/7] Add PCIe support to Sophgo SG2042 SoC Chen Wang
@ 2025-09-19 18:24 ` Manivannan Sadhasivam
8 siblings, 0 replies; 12+ messages in thread
From: Manivannan Sadhasivam @ 2025-09-19 18:24 UTC (permalink / raw)
To: kwilczynski, u.kleine-koenig, aou, alex, arnd, bwawrzyn, bhelgaas,
unicorn_wang, conor+dt, 18255117159, inochiama, kishon, krzk+dt,
lpieralisi, palmer, paul.walmsley, robh, s-vadapalli, tglx,
thomas.richard, sycamoremoon376, devicetree, linux-kernel,
linux-pci, linux-riscv, sophgo, rabenda.cn, chao.wei,
xiaoguang.xing, fengchun.li, jeffbai, Chen Wang
On Fri, 12 Sep 2025 10:35:10 +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@outlook.com>
>
> Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode.
>
> This is a completely rewritten PCIe driver for SG2042. It inherits
> some previously submitted patch codes (not merged into the upstream
> mainline), but the biggest difference is that the support for
> compatibility with old 32-bit PCIe devices has been removed in this
> new version. This is because after discussing with community users,
> we felt that there was not much demand for support for old devices,
> so we made a new design based on the simplified design and practical
> needs. If someone really needs to play with old devices, we can provide
> them with some necessary hack patches in the downstream repository.
>
> [...]
Applied, thanks!
[1/7] dt-bindings: pci: Add Sophgo SG2042 PCIe host
commit: 4e4a4f58bed19e1a3a5a7c3a18ce3b927b76fcd3
[2/7] PCI: cadence: Check pcie-ops before using it
commit: 49a6c160ad4812476f8ae1a8f4ed6d15adfa6c09
[3/7] PCI: sg2042: Add Sophgo SG2042 PCIe driver
commit: 1c72774df028429836eec3394212f2921bb830fc
Best regards,
--
Manivannan Sadhasivam <mani@kernel.org>
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