[PATCH v5 0/2] Enable Service layer driver for Agilex5

[PATCH v5 0/2] Enable Service layer driver for Agilex5

[Khairul Anuar Romli]

This patch series introduces support for the Agilex5 service layer driver
(SVC) in the Linux kernel. The changes span across device tree bindings,
platform DTS files, and the Stratix10 SVC firmware driver.

These changes are necessary to enable firmware communication on Agilex5
SoCs via the SVC interface, similar to existing support for Stratix10 and
Agilex platforms.

Agilex5 introduces the ability for the TBU to operate in non-secure mode,
making it accessible to Linux through the IOMMU framework. This key
difference enables improved memory management in non-secure environments.
As a result, this series extends the SVC driver and device tree bindings
to support IOMMU integration for Agilex5.
---
Notes:
This patch series is applied on socfpga maintainer's tree
https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19

Changes in v5:
	- Use contains enum instead of const
Changes in v4:
	- Refactor the logical check without using AllOf.
Changes in v3:
	- Remove driver changes in driver as it is fully compatible
	- Add iommu entry and rewrite the git commit message to describe
	  why the changes is required.
Changes in v2:
	- Add driver changes for Agilex5-svc compatible
---
Khairul Anuar Romli (2):
  dt-bindings: firmware: svc: Add IOMMU support for Agilex5
  arm64: dts: intel: Add Agilex5 SVC node with memory region

 .../bindings/firmware/intel,stratix10-svc.yaml     | 14 ++++++++++++++
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi     |  9 +++++++++
 2 files changed, 23 insertions(+)

-- 
2.43.7

[PATCH v5 1/2] dt-bindings: firmware: svc: Add IOMMU support for Agilex5

[Khairul Anuar Romli]

In Agilex5, the TBU (Translation Buffer Unit) can now operate in non-secure
mode, enabling Linux to utilize it through the IOMMU framework. This allows
improved memory management capabilities in non-secure environments. With
Agilex5 lifting this restriction, we are now extending the device tree
bindings to support IOMMU for the Agilex5 SVC.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v5:
	- Use contains enum instead of const
Changes in v4:
	- Fix syntax / style error.
	- Refactor code not to use AllOf but instead use if directly.
Changes in v3:
	- Add iommu property.
	- Add logical check where only Agilex5 required iommus
	- Rewrite the commit message to explain why this changes is 
	  needed.
Changes in v2:
	- Reprase commit message to exclude iommu
---
 .../bindings/firmware/intel,stratix10-svc.yaml     | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
index fac1e955852e..a66aeed0ddee 100644
--- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
+++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
@@ -34,6 +34,7 @@ properties:
     enum:
       - intel,stratix10-svc
       - intel,agilex-svc
+      - intel,agilex5-svc
 
   method:
     description: |
@@ -54,6 +55,9 @@ properties:
       reserved memory region for the service layer driver to
       communicate with the secure device manager.
 
+  iommus:
+    maxItems: 1
+
   fpga-mgr:
     $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml
     description: Optional child node for fpga manager to perform fabric configuration.
@@ -63,6 +67,16 @@ required:
   - method
   - memory-region
 
+if:
+  properties:
+    compatible:
+      contains:
+        enum:
+          - intel,agilex5-svc
+then:
+  required:
+    - iommus
+
 additionalProperties: false
 
 examples:
-- 
2.43.7

[PATCH v5 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region

[Khairul Anuar Romli]

Introduce the Stratix10 SoC Service Layer (SVC) node for Agilex5 SoCs. This
node includes the compatible string "intel,agilex5-svc" and references a
reserved memory region used for communication with the Secure Device
Manager (SDM).

Agilex5 introduces changes in how reserved memory is mapped and accessed
compared to previous SoC generations, particularly with the addition of
IOMMU support. Unlike earlier platforms, Agilex5 enables the use of the
Translation Buffer Unit (TBU) in non-secure mode, allowing Linux to access
it through the IOMMU framework. This commit updates the device tree
structure to support Agilex5-specific handling of the SVC interface,
including the necessary bindings for IOMMU integration.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
Changes in v5:
	- No change.
Changes in v4:
	- Exclude peers reviewers in the sign off.
Changes in v3:
	- include iommu property in svc node.
	- Rephrase git commit message to describe iommu presence
	  in Agilex5
Changes in v2:
	- Rephrase commit message to exclude mentioning iommu
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a13ccee3c4c3..15284092897e 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -841,5 +841,14 @@ queue7 {
 				};
 			};
 		};
+
+		firmware {
+			svc {
+				compatible = "intel,agilex5-svc";
+				method = "smc";
+				memory-region = <&service_reserved>;
+				iommus = <&smmu 10>;
+			};
+		};
 	};
 };
-- 
2.43.7

Re: [PATCH v5 1/2] dt-bindings: firmware: svc: Add IOMMU support for Agilex5

[Krzysztof Kozlowski]

On Wed, Nov 05, 2025 at 10:28:01AM +0800, Khairul Anuar Romli wrote:
> In Agilex5, the TBU (Translation Buffer Unit) can now operate in non-secure
> mode, enabling Linux to utilize it through the IOMMU framework. This allows
> improved memory management capabilities in non-secure environments. With
> Agilex5 lifting this restriction, we are now extending the device tree
> bindings to support IOMMU for the Agilex5 SVC.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v5:
> 	- Use contains enum instead of const
> Changes in v4:
> 	- Fix syntax / style error.
> 	- Refactor code not to use AllOf but instead use if directly.

Why? I would expect there allOf, so you won't re-indent when next
if:then: clause comes.

Anyway, slow down with your patches - one posting per 24h. That's like
three versions within that timeframe...


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v5 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region

[Krzysztof Kozlowski]

On Wed, Nov 05, 2025 at 10:28:02AM +0800, Khairul Anuar Romli wrote:
> Introduce the Stratix10 SoC Service Layer (SVC) node for Agilex5 SoCs. This
> node includes the compatible string "intel,agilex5-svc" and references a
> reserved memory region used for communication with the Secure Device
> Manager (SDM).
> 
> Agilex5 introduces changes in how reserved memory is mapped and accessed
> compared to previous SoC generations, particularly with the addition of
> IOMMU support. Unlike earlier platforms, Agilex5 enables the use of the
> Translation Buffer Unit (TBU) in non-secure mode, allowing Linux to access
> it through the IOMMU framework. This commit updates the device tree
> structure to support Agilex5-specific handling of the SVC interface,
> including the necessary bindings for IOMMU integration.
> 
> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
> ---
> Changes in v5:
> 	- No change.
> Changes in v4:
> 	- Exclude peers reviewers in the sign off.
> Changes in v3:
> 	- include iommu property in svc node.
> 	- Rephrase git commit message to describe iommu presence
> 	  in Agilex5
> Changes in v2:
> 	- Rephrase commit message to exclude mentioning iommu
> ---
>  arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index a13ccee3c4c3..15284092897e 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -841,5 +841,14 @@ queue7 {
>  				};
>  			};
>  		};
> +
> +		firmware {

Did you just add node to the end of the file? No. Place it somewhere
after cpus, see DTS coding style.

Another problem that you have here warnings, which tools would tell you.
Please use tools instead of humans, see maintainer soc profiles (both)
for more explanation.

Best regards,
Krzysztof

Re: [PATCH v5 1/2] dt-bindings: firmware: svc: Add IOMMU support for Agilex5

[Romli, Khairul Anuar]

On 5/11/2025 4:23 pm, Krzysztof Kozlowski wrote:
> On Wed, Nov 05, 2025 at 10:28:01AM +0800, Khairul Anuar Romli wrote:
>> In Agilex5, the TBU (Translation Buffer Unit) can now operate in non-secure
>> mode, enabling Linux to utilize it through the IOMMU framework. This allows
>> improved memory management capabilities in non-secure environments. With
>> Agilex5 lifting this restriction, we are now extending the device tree
>> bindings to support IOMMU for the Agilex5 SVC.
>>
>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>> ---
>> Changes in v5:
>> 	- Use contains enum instead of const
>> Changes in v4:
>> 	- Fix syntax / style error.
>> 	- Refactor code not to use AllOf but instead use if directly.
> 
> Why? I would expect there allOf, so you won't re-indent when next
> if:then: clause comes.
> 
Sure, I will put back the AllOf so that the future changes that require 
different property can be added within that block.

> Anyway, slow down with your patches - one posting per 24h. That's like
> three versions within that timeframe...

Sure, I will slow down to send the next version.

> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
Can I add this in my next version?

> Best regards,
> Krzysztof
> 

Re: [PATCH v5 2/2] arm64: dts: intel: Add Agilex5 SVC node with memory region

[Romli, Khairul Anuar]

On 5/11/2025 4:25 pm, Krzysztof Kozlowski wrote:
> On Wed, Nov 05, 2025 at 10:28:02AM +0800, Khairul Anuar Romli wrote:
>> Introduce the Stratix10 SoC Service Layer (SVC) node for Agilex5 SoCs. This
>> node includes the compatible string "intel,agilex5-svc" and references a
>> reserved memory region used for communication with the Secure Device
>> Manager (SDM).
>>
>> Agilex5 introduces changes in how reserved memory is mapped and accessed
>> compared to previous SoC generations, particularly with the addition of
>> IOMMU support. Unlike earlier platforms, Agilex5 enables the use of the
>> Translation Buffer Unit (TBU) in non-secure mode, allowing Linux to access
>> it through the IOMMU framework. This commit updates the device tree
>> structure to support Agilex5-specific handling of the SVC interface,
>> including the necessary bindings for IOMMU integration.
>>
>> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
>> ---
>> Changes in v5:
>> 	- No change.
>> Changes in v4:
>> 	- Exclude peers reviewers in the sign off.
>> Changes in v3:
>> 	- include iommu property in svc node.
>> 	- Rephrase git commit message to describe iommu presence
>> 	  in Agilex5
>> Changes in v2:
>> 	- Rephrase commit message to exclude mentioning iommu
>> ---
>>   arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 9 +++++++++
>>   1 file changed, 9 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> index a13ccee3c4c3..15284092897e 100644
>> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> @@ -841,5 +841,14 @@ queue7 {
>>   				};
>>   			};
>>   		};
>> +
>> +		firmware {
> 
> Did you just add node to the end of the file? No. Place it somewhere
> after cpus, see DTS coding style.
> 
Noted. I will place this node after cpu to make it consistent with 
Agilex dts.
> Another problem that you have here warnings, which tools would tell you.
> Please use tools instead of humans, see maintainer soc profiles (both)
> for more explanation.
>
I use make DTC_FLAGS=-@ intel/socfpga_agilex5_socdk.dtb to check for the 
warning but my thought was those are not related. Now I test again 
without the firmware the changes and run the build command, I do see it 
is clean without the changes.

I will fix this one and ensure the build is warning free.

Thanks.

Regards,
Khairul
> Best regards,
> Krzysztof
>