[PATCH v3 0/3] Add dma-coherent property

[PATCH v3 0/3] Add dma-coherent property

[Khairul Anuar Romli]

This patch series adds dma-coherent property for the Agilex5 platform by:

- Updating the device tree bindings for:
  - Cadence HP NAND controller (`cdns,hp-nfc`)
  - Synopsys DesignWare AXI DMA controller (`snps,dw-axi-dmac`)
  to accept the `dma-coherent` property.

- Adding the dma-coherent property to the Agilex5 device tree and wiring up
  the property to the supported peripherals:
  - NAND controller
  - DMA controller

This dma-coherent addition aligns the Agilex5 platform with ARM’s
architectural requirements for coherent interconnects.

---
Notes:
This patch series is applied and validated on socfpga dts maintainer's
branch
https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19

This changes is validated on:
	- intel/socfpga_agilex5_socdk.dtb
	- snps,dw-axi-dmac.yaml
	- snps,dw-axi-dmac.yaml intel/socfpga_agilex5_socdk.dtb 
	- cdns,hp-nfc.yaml 
	- cdns,hp-nfc.yaml intel/socfpga_agilex5_socdk.dtb 
---
Khairul Anuar Romli (3):
  dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property
  dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property
  arm64: dts: socfpga: agilex5: Add dma-coherent property

 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
 Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml      | 2 ++
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi              | 3 +++
 3 files changed, 7 insertions(+)

-- 
2.43.7

[PATCH 1/3] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property

[Khairul Anuar Romli]

The Cadence HP NAND Flash Controller on Agilex5 device performs DMA
transactions through a coherent interconnect. dma-coherent property
presents in device tree will allow the kernel’s DMA subsystem
controller’s to performs DMA transaction in dma coherent mode.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
 Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
index 73dc69cee4d8..367257a227b1 100644
--- a/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
+++ b/Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml
@@ -40,6 +40,8 @@ properties:
   dmas:
     maxItems: 1
 
+  dma-coherent: true
+
   iommus:
     maxItems: 1
 
-- 
2.43.7

[PATCH 2/3] dt-bindings: dma: snps,dw-axi-dmac: add dma-coherent property

[Khairul Anuar Romli]

The Synopsys DesignWare AXI DMA Controller on Agilex5, the controller
operates on a cache-coherent AXI interface, where DMA transactions are
automatically kept coherent with the CPU caches.

dma-coherent property will enable operating system to performs DMA
transactions in dma coherent mode.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index a393a33c8908..eb67348b4ab1 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -64,6 +64,8 @@ properties:
 
   dma-noncoherent: true
 
+  dma-coherent: true
+
   resets:
     minItems: 1
     maxItems: 2
-- 
2.43.7

[PATCH 3/3] arm64: dts: socfpga: agilex5: Add dma-coherent property

[Khairul Anuar Romli]

Add the `dma-coherent` property to these device nodes to inform the
kernel and DMA subsystem that the devices support hardware-managed
cache coherence.

Changes:
 - Add `dma-coherent` to `cdns,hp-nfc`
 - Add `dma-coherent` to both `snps,axi-dma-1.01a` instances
   (dmac0, dmac1)

This aligns the Agilex5 device tree with the coherent DMA-capable
devices accordingly.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 1f5d560f97b2..d6a2fe445fa6 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -324,6 +324,7 @@ nand: nand-controller@10b80000 {
 			clock-names = "nf_clk";
 			cdns,board-delay-ps = <4830>;
 			iommus = <&smmu 4>;
+			dma-coherent;
 			status = "disabled";
 		};
 
@@ -351,6 +352,7 @@ dmac0: dma-controller@10db0000 {
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <8>;
 			iommus = <&smmu 8>;
+			dma-coherent;
 		};
 
 		dmac1: dma-controller@10dc0000 {
@@ -369,6 +371,7 @@ dmac1: dma-controller@10dc0000 {
 			snps,priority = <0 1 2 3>;
 			snps,axi-max-burst-len = <8>;
 			iommus = <&smmu 9>;
+			dma-coherent;
 		};
 
 		rst: rstmgr@10d11000 {
-- 
2.43.7

Re: [PATCH 1/3] dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property

[Krzysztof Kozlowski]

On Wed, Nov 26, 2025 at 04:06:22PM +0800, Khairul Anuar Romli wrote:
> The Cadence HP NAND Flash Controller on Agilex5 device performs DMA
> transactions through a coherent interconnect. dma-coherent property
> presents in device tree will allow the kernel’s DMA subsystem
> controller’s to performs DMA transaction in dma coherent mode.

Last sentence is redundant. You say basically "dma-coherent means
dma coherent". Write informative commit msgs, so something which is not
obvious, e.g. why this is dma coherent NOW but wasn't before?

Best regards,
Krzysztof