[PATCH v2 0/4] Add Altera Agilex5 DWC3 support

[PATCH v2 0/4] Add Altera Agilex5 DWC3 support

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Agilex5 integrates a Synopsys DesignWare USB3 controller via a
SoC-specific wrapper that requires dedicated clock, reset, PHY, and
optional SMMU integration. In addition, the Agilex5 has a 40-bit DMA 
address bus limitation. When SMMU is enabled, using the default 64-bit
DMA mask can result in address truncation and subsequent translation
faults. This series addresses that limitation by allowing the glue
driver to constrain the DMA mask appropriately.

This series adds a device tree binding for the Agilex5 DWC3 wrapper and
introduces the corresponding USB3.1 controller node in the Agilex5 SoC
and SoCDK device trees. As the SoCDK only exposes the USB3.1 interface,
the unused USB0 node is removed. The series also extends the dwc3
generic platform driver with Agilex5-specific configuration support,
including limiting the DMA addressable width to 40 bits to avoid DMA
faults when SMMU is enabled.

---
changelog:
v1->v2:
* Update new binding name to match compatible.
* Update binding to use single node instead of parent child node structure.
* Update binding according to comments from maintainer.
* Split USB3 and USB2 changes in dts into separate commits.
* Update to use flattened model and use dwc3-generic-plat driver instead of
  dwc3-of-simple driver.
* Add dma_addressable_bits as a dwc3 property which is set by the glue driver
  which is used to configure the dma mask in the core driver.

v1 patch link:
https://lore.kernel.org/all/cover.1762839776.git.adrianhoyin.ng@altera.com/
---

Adrian Ng Ho Yin (4):
  dt-bindings: usb: dwc3: Add support for Altera Agilex5 DWC3
  arm64: dts: intel: agilex5: Add USB3.1 support for Agilex5 SoCDK
  arm64: dts: intel: agilex5: Remove usb0 in Agilex5 SoCDK
  usb: dwc3: Add support for Agilex5 in dwc3-generic-platform driver

 .../bindings/usb/altr,agilex5-dwc3.yaml       | 96 +++++++++++++++++++
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 18 ++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  4 +-
 drivers/usb/dwc3/core.c                       |  6 +-
 drivers/usb/dwc3/core.h                       |  5 +
 drivers/usb/dwc3/dwc3-generic-plat.c          | 20 +++-
 6 files changed, 145 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml

-- 
2.49.GIT

[PATCH v2 1/4] dt-bindings: usb: dwc3: Add support for Altera Agilex5 DWC3

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add device tree binding for the Synopsys DesignWare USB3 (DWC3) controller
on Altera Agilex5 SoC. The binding describes SoC-specific integration
including clock and reset control for the USB subsystem.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 .../bindings/usb/altr,agilex5-dwc3.yaml       | 96 +++++++++++++++++++
 1 file changed, 96 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml

diff --git a/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
new file mode 100644
index 000000000000..d40719e0e49d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/altr,agilex5-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera Agilex5 DWC3 USB SoC Controller Wrapper
+
+maintainers:
+  - Adrian Ng <adrianhoyin.ng@altera.com>
+
+description:
+  The Altera Agilex5 SoCFPGA integrates a Synopsys DesignWare USB3 (DWC3)
+  controller that supports host, device and DRD modes. This binding describes
+  SoC integration including clocks, resets, PHY connections, and optional
+  IOMMU support.
+
+allOf:
+  - $ref: snps,dwc3-common.yaml#
+
+properties:
+  compatible:
+    const: altr,agilex5-dwc3
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: Controller suspend clock
+      - description: Master/Core bus clock
+
+  clock-names:
+    items:
+      - const: suspend_clk
+      - const: bus_clk
+
+  interrupts:
+    maxItems: 1
+
+  phys:
+    items:
+      - description: USB2 PHY
+      - description: USB3 PHY
+
+  phy-names:
+    items:
+      - const: usb2-phy
+      - const: usb3-phy
+
+  iommus:
+    maxItems: 1
+
+  resets:
+    items:
+      - description: DWC3 core reset
+      - description: DWC3 ECC reset
+
+  reset-names:
+    items:
+      - const: dwc3
+      - const: dwc3-ecc
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - interrupts
+  - phys
+  - phy-names
+  - resets
+  - reset-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/reset/altr,rst-mgr-s10.h>
+    #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
+
+    usb31: usb@11000000 {
+        compatible = "altr,agilex5-dwc3";
+        reg = <0x11000000 0x100000>;
+        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
+                 <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>;
+        clock-names = "suspend_clk", "bus_clk";
+        phys = <&usbphy0>, <&usbphy1>;
+        phy-names = "usb2-phy", "usb3-phy";
+        resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+        reset-names = "dwc3", "dwc3-ecc";
+        iommus = <&smmu 7>;
+        dr_mode = "host";
+    };
-- 
2.49.GIT

Re: [PATCH v2 1/4] dt-bindings: usb: dwc3: Add support for Altera Agilex5 DWC3

[Rob Herring]

On Tue, Dec 09, 2025 at 02:25:08PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add device tree binding for the Synopsys DesignWare USB3 (DWC3) controller
> on Altera Agilex5 SoC. The binding describes SoC-specific integration
> including clock and reset control for the USB subsystem.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
>  .../bindings/usb/altr,agilex5-dwc3.yaml       | 96 +++++++++++++++++++
>  1 file changed, 96 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
> 
> diff --git a/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
> new file mode 100644
> index 000000000000..d40719e0e49d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/altr,agilex5-dwc3.yaml
> @@ -0,0 +1,96 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/altr,agilex5-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera Agilex5 DWC3 USB SoC Controller Wrapper
> +
> +maintainers:
> +  - Adrian Ng <adrianhoyin.ng@altera.com>
> +
> +description:
> +  The Altera Agilex5 SoCFPGA integrates a Synopsys DesignWare USB3 (DWC3)
> +  controller that supports host, device and DRD modes. This binding describes
> +  SoC integration including clocks, resets, PHY connections, and optional
> +  IOMMU support.
> +
> +allOf:
> +  - $ref: snps,dwc3-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: altr,agilex5-dwc3
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: Controller suspend clock
> +      - description: Master/Core bus clock
> +
> +  clock-names:
> +    items:
> +      - const: suspend_clk
> +      - const: bus_clk

Don't invent new names. The common names are 'suspend' and 'bus_early'.

Sure there is no 'ref' clock too?

> +
> +  interrupts:
> +    maxItems: 1
> +
> +  phys:
> +    items:
> +      - description: USB2 PHY
> +      - description: USB3 PHY
> +
> +  phy-names:
> +    items:
> +      - const: usb2-phy
> +      - const: usb3-phy
> +
> +  iommus:
> +    maxItems: 1
> +
> +  resets:
> +    items:
> +      - description: DWC3 core reset
> +      - description: DWC3 ECC reset
> +
> +  reset-names:
> +    items:
> +      - const: dwc3
> +      - const: dwc3-ecc
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - phys
> +  - phy-names
> +  - resets
> +  - reset-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/reset/altr,rst-mgr-s10.h>
> +    #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
> +
> +    usb31: usb@11000000 {

Drop unused labels.

> +        compatible = "altr,agilex5-dwc3";
> +        reg = <0x11000000 0x100000>;
> +        interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
> +        clocks = <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
> +                 <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>;
> +        clock-names = "suspend_clk", "bus_clk";
> +        phys = <&usbphy0>, <&usbphy1>;
> +        phy-names = "usb2-phy", "usb3-phy";
> +        resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
> +        reset-names = "dwc3", "dwc3-ecc";
> +        iommus = <&smmu 7>;
> +        dr_mode = "host";
> +    };
> -- 
> 2.49.GIT
> 

[PATCH v2 2/4] arm64: dts: intel: agilex5: Add USB3.1 support for Agilex5 SoCDK

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add usb3 node for the USB3.1 controller on the Agilex5 SoC and enable
it on the SoCDK board.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 18 ++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts   |  5 +++++
 2 files changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a5c2025a616e..226e4f0a2439 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -483,6 +483,24 @@ usb0: usb@10b00000 {
 			status = "disabled";
 		};
 
+		usb31: usb1@11000000 {
+			compatible = "altr,agilex5-dwc3";
+			reg = <0x11000000 0x100000>;
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
+				 <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>;
+			clock-names = "suspend_clk", "bus_clk";
+			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+			reset-names = "dwc3", "dwc3-ecc";
+			iommus = <&smmu 7>;
+			phys = <&usbphy0>, <&usbphy0>;
+			phy-names = "usb2-phy", "usb3-phy";
+			maximum-speed = "super-speed";
+			snps,dis_u2_susphy_quirk;
+			snps,dis_u3_susphy_quirk;
+			status = "disabled";
+		};
+
 		watchdog0: watchdog@10d00200 {
 			compatible = "snps,dw-wdt";
 			reg = <0x10d00200 0x100>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 262bb3e8e5c7..3f5b116120fd 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -107,6 +107,11 @@ &usb0 {
 	disable-over-current;
 };
 
+&usb31 {
+	dr_mode = "host";
+	status = "okay";
+};
+
 &watchdog0 {
 	status = "okay";
 };
-- 
2.49.GIT

[PATCH v2 3/4] arm64: dts: intel: agilex5: Remove usb0 in Agilex5 SoCDK

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

The Agilex5 SoCDK daughter card only provides a USB3.1 interface (USB1).
USB0 is not connected or used on this board. Removing the USB0 node to
avoid unnecessary initialization and potential resource conflicts.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 3f5b116120fd..e10bfda1a440 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -102,11 +102,6 @@ &uart0 {
 	status = "okay";
 };
 
-&usb0 {
-	status = "okay";
-	disable-over-current;
-};
-
 &usb31 {
 	dr_mode = "host";
 	status = "okay";
-- 
2.49.GIT

[PATCH v2 4/4] usb: dwc3: Add support for Agilex5 in dwc3-generic-platform driver

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Adds support for Agilex5 in the dwc3-generic-platform driver. Extends
generic driver to support configurable driver data to enable dwc3 core
property configuration from glue driver.

Agilex5 DWC3 wrapper has a 40-bit DMA address bus limitation. When SMMU
is enabled, using the default 64-bit DMA mask can cause DMA addresses to
be truncated, leading to translation faults.

This patch adds a `dma_addressable_bits` field in struct dwc3, allowing
the glue driver to set a 40-bit DMA mask during probe.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 drivers/usb/dwc3/core.c              |  6 +++++-
 drivers/usb/dwc3/core.h              |  5 +++++
 drivers/usb/dwc3/dwc3-generic-plat.c | 20 +++++++++++++++++++-
 3 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ae140c356295..1fca55637844 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -2243,7 +2243,11 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
 
 	if (!dwc->sysdev_is_parent &&
 	    DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
-		ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
+		if (!dwc->dma_addressable_bits)
+			dwc->dma_addressable_bits = 64;
+
+		ret = dma_set_mask_and_coherent(dwc->sysdev,
+						DMA_BIT_MASK(dwc->dma_addressable_bits));
 		if (ret)
 			goto err_disable_clks;
 	}
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index a5fc92c4ffa3..a09800fe6577 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1180,6 +1180,10 @@ struct dwc3_glue_ops {
  * @wakeup_pending_funcs: Indicates whether any interface has requested for
  *			 function wakeup in bitmap format where bit position
  *			 represents interface_id.
+ * @dma_addressable_bits: The number of address bits the device can drive on
+ *			the DMA bus. The driver uses this value to program DMA masks and
+ *			ensure DMA buffers are allocated within the device’s reachable
+ *			address space.
  */
 struct dwc3 {
 	struct work_struct	drd_work;
@@ -1414,6 +1418,7 @@ struct dwc3 {
 	struct dentry		*debug_root;
 	u32			gsbuscfg0_reqinfo;
 	u32			wakeup_pending_funcs;
+	u32			dma_addressable_bits;
 };
 
 #define INCRX_BURST_MODE 0
diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
index d96b20570002..e9650df6cf81 100644
--- a/drivers/usb/dwc3/dwc3-generic-plat.c
+++ b/drivers/usb/dwc3/dwc3-generic-plat.c
@@ -20,6 +20,11 @@ struct dwc3_generic {
 	struct reset_control	*resets;
 };
 
+struct dwc3_generic_config {
+	u32 flags;
+};
+
+#define DWC3_HAS_40BIT_DMA_QUIRK BIT(0)
 #define to_dwc3_generic(d) container_of((d), struct dwc3_generic, dwc)
 
 static void dwc3_generic_reset_control_assert(void *data)
@@ -34,6 +39,7 @@ static int dwc3_generic_probe(struct platform_device *pdev)
 	struct dwc3_generic *dwc3g;
 	struct resource *res;
 	int ret;
+	const struct dwc3_generic_config *drvdata;
 
 	dwc3g = devm_kzalloc(dev, sizeof(*dwc3g), GFP_KERNEL);
 	if (!dwc3g)
@@ -70,6 +76,10 @@ static int dwc3_generic_probe(struct platform_device *pdev)
 	if (ret < 0)
 		return dev_err_probe(dev, ret, "failed to get clocks\n");
 
+	drvdata = device_get_match_data(dev);
+	if (drvdata && (drvdata->flags & DWC3_HAS_40BIT_DMA_QUIRK))
+		dwc3g->dwc.dma_addressable_bits = 40;
+
 	dwc3g->num_clocks = ret;
 	dwc3g->dwc.dev = dev;
 	probe_data.dwc = &dwc3g->dwc;
@@ -145,8 +155,16 @@ static const struct dev_pm_ops dwc3_generic_dev_pm_ops = {
 		       dwc3_generic_runtime_idle)
 };
 
+static const struct dwc3_generic_config agilex5_config = {
+	.flags = DWC3_HAS_40BIT_DMA_QUIRK,
+};
+
 static const struct of_device_id dwc3_generic_of_match[] = {
-	{ .compatible = "spacemit,k1-dwc3", },
+	{	.compatible = "spacemit,k1-dwc3", },
+	{
+		.compatible = "altr,agilex5-dwc3",
+		.data = &agilex5_config,
+	},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, dwc3_generic_of_match);
-- 
2.49.GIT

Re: [PATCH v2 4/4] usb: dwc3: Add support for Agilex5 in dwc3-generic-platform driver

[Rob Herring]

On Tue, Dec 09, 2025 at 02:25:11PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Adds support for Agilex5 in the dwc3-generic-platform driver. Extends
> generic driver to support configurable driver data to enable dwc3 core
> property configuration from glue driver.
> 
> Agilex5 DWC3 wrapper has a 40-bit DMA address bus limitation. When SMMU
> is enabled, using the default 64-bit DMA mask can cause DMA addresses to
> be truncated, leading to translation faults.
> 
> This patch adds a `dma_addressable_bits` field in struct dwc3, allowing
> the glue driver to set a 40-bit DMA mask during probe.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
>  drivers/usb/dwc3/core.c              |  6 +++++-
>  drivers/usb/dwc3/core.h              |  5 +++++
>  drivers/usb/dwc3/dwc3-generic-plat.c | 20 +++++++++++++++++++-
>  3 files changed, 29 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index ae140c356295..1fca55637844 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -2243,7 +2243,11 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
>  
>  	if (!dwc->sysdev_is_parent &&
>  	    DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
> -		ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
> +		if (!dwc->dma_addressable_bits)
> +			dwc->dma_addressable_bits = 64;
> +
> +		ret = dma_set_mask_and_coherent(dwc->sysdev,
> +						DMA_BIT_MASK(dwc->dma_addressable_bits));
>  		if (ret)
>  			goto err_disable_clks;
>  	}
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index a5fc92c4ffa3..a09800fe6577 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -1180,6 +1180,10 @@ struct dwc3_glue_ops {
>   * @wakeup_pending_funcs: Indicates whether any interface has requested for
>   *			 function wakeup in bitmap format where bit position
>   *			 represents interface_id.
> + * @dma_addressable_bits: The number of address bits the device can drive on
> + *			the DMA bus. The driver uses this value to program DMA masks and
> + *			ensure DMA buffers are allocated within the device’s reachable
> + *			address space.
>   */
>  struct dwc3 {
>  	struct work_struct	drd_work;
> @@ -1414,6 +1418,7 @@ struct dwc3 {
>  	struct dentry		*debug_root;
>  	u32			gsbuscfg0_reqinfo;
>  	u32			wakeup_pending_funcs;
> +	u32			dma_addressable_bits;
>  };
>  
>  #define INCRX_BURST_MODE 0
> diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
> index d96b20570002..e9650df6cf81 100644
> --- a/drivers/usb/dwc3/dwc3-generic-plat.c
> +++ b/drivers/usb/dwc3/dwc3-generic-plat.c
> @@ -20,6 +20,11 @@ struct dwc3_generic {
>  	struct reset_control	*resets;
>  };
>  
> +struct dwc3_generic_config {
> +	u32 flags;
> +};
> +
> +#define DWC3_HAS_40BIT_DMA_QUIRK BIT(0)

Quirk flags are good, but if we have 10 different address sizes that's 
10 flags. Just make a dma_addressable_bits field here too, and then it 
is just a straight assignment.

Rob

Re: [PATCH v2 4/4] usb: dwc3: Add support for Agilex5 in dwc3-generic-platform driver

[Thinh Nguyen]

On Tue, Dec 09, 2025, Rob Herring wrote:
> On Tue, Dec 09, 2025 at 02:25:11PM +0800, adrianhoyin.ng@altera.com wrote:
> > From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> > 
> > Adds support for Agilex5 in the dwc3-generic-platform driver. Extends
> > generic driver to support configurable driver data to enable dwc3 core
> > property configuration from glue driver.
> > 
> > Agilex5 DWC3 wrapper has a 40-bit DMA address bus limitation. When SMMU
> > is enabled, using the default 64-bit DMA mask can cause DMA addresses to
> > be truncated, leading to translation faults.
> > 
> > This patch adds a `dma_addressable_bits` field in struct dwc3, allowing
> > the glue driver to set a 40-bit DMA mask during probe.
> > 
> > Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> > ---
> >  drivers/usb/dwc3/core.c              |  6 +++++-
> >  drivers/usb/dwc3/core.h              |  5 +++++
> >  drivers/usb/dwc3/dwc3-generic-plat.c | 20 +++++++++++++++++++-
> >  3 files changed, 29 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > index ae140c356295..1fca55637844 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -2243,7 +2243,11 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
> >  
> >  	if (!dwc->sysdev_is_parent &&
> >  	    DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
> > -		ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
> > +		if (!dwc->dma_addressable_bits)
> > +			dwc->dma_addressable_bits = 64;
> > +
> > +		ret = dma_set_mask_and_coherent(dwc->sysdev,
> > +						DMA_BIT_MASK(dwc->dma_addressable_bits));
> >  		if (ret)
> >  			goto err_disable_clks;
> >  	}
> > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> > index a5fc92c4ffa3..a09800fe6577 100644
> > --- a/drivers/usb/dwc3/core.h
> > +++ b/drivers/usb/dwc3/core.h
> > @@ -1180,6 +1180,10 @@ struct dwc3_glue_ops {
> >   * @wakeup_pending_funcs: Indicates whether any interface has requested for
> >   *			 function wakeup in bitmap format where bit position
> >   *			 represents interface_id.
> > + * @dma_addressable_bits: The number of address bits the device can drive on
> > + *			the DMA bus. The driver uses this value to program DMA masks and
> > + *			ensure DMA buffers are allocated within the device’s reachable
> > + *			address space.
> >   */
> >  struct dwc3 {
> >  	struct work_struct	drd_work;
> > @@ -1414,6 +1418,7 @@ struct dwc3 {
> >  	struct dentry		*debug_root;
> >  	u32			gsbuscfg0_reqinfo;
> >  	u32			wakeup_pending_funcs;
> > +	u32			dma_addressable_bits;
> >  };
> >  
> >  #define INCRX_BURST_MODE 0
> > diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
> > index d96b20570002..e9650df6cf81 100644
> > --- a/drivers/usb/dwc3/dwc3-generic-plat.c
> > +++ b/drivers/usb/dwc3/dwc3-generic-plat.c
> > @@ -20,6 +20,11 @@ struct dwc3_generic {
> >  	struct reset_control	*resets;
> >  };
> >  
> > +struct dwc3_generic_config {
> > +	u32 flags;
> > +};
> > +
> > +#define DWC3_HAS_40BIT_DMA_QUIRK BIT(0)
> 
> Quirk flags are good, but if we have 10 different address sizes that's 
> 10 flags. Just make a dma_addressable_bits field here too, and then it 
> is just a straight assignment.
> 

Right, don't create new quirk flag for this. Pass as a dwc3 property to
the core.

See how that is done here:
https://lore.kernel.org/linux-usb/20251112055346.1655-1-caohang@eswincomputing.com/

However, I don't think the above is applied to mainline yet.

BR,
Thinh