[PATCH 0/2] Add FPGA configuration and partial reconfiguration support for Agilex5

[Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>]

This series enables FPGA configuration and partial reconfiguration on Altera Agilex5 SoC.

On Agilex5 the DDR base address starts at 0x8000_0000, which is
outside the addressable range of the SDM. The SMMU is used to remap
DDR-allocated buffers to an IOVA within the SDM-accessible 0-512MB
window. Agilex5 REV B introduced a hardware SDM address remapper,
but it must be bypassed so no additional offset is applied to the
IOVA, keeping the implementation consistent across all Agilex5
revisions.

Patch 1 adds the fpga-mgr child node and fpga-region to the Agilex5
DTSI and enables the SMMU, which is always required on Agilex5 for
the service layer to operate correctly.

Patch 2 extends the stratix10-svc driver to support the new
intel,agilex5-svc compatible. It enforces SMMU presence at probe,
configures a 29-bit DMA mask, and bypasses the SDM address remapper
via SMC. The driver adds 0x8000_0000 to each IOVA before the SMC
call so the address passes ATF's is_address_in_ddr_range() check;
the firmware COMPLETED_WRITE response returns the raw IOVA, so the
offset is added back before the svc_pa_to_va() lookup. It also
fixes a pre-existing list corruption bug in
stratix10_svc_free_memory() and adds a devm cleanup action to
reclaim leaked buffers on driver unbind.

Adrian Ng Ho Yin (2):
  arm64: dts: socfpga: agilex5: add FPGA manager and region nodes
  firmware: stratix10-svc: add support for agilex5

 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi |  12 +-
 drivers/firmware/stratix10-svc.c              | 258 +++++++++++++++---
 include/linux/firmware/intel/stratix10-smc.h  |  23 ++
 3 files changed, 248 insertions(+), 45 deletions(-)

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2.49.GIT