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Sun, 2 Aug 2026 11:31:02 +0000 Date: Sun, 2 Aug 2026 11:30:44 +0000 From: Rudi Heitbaum To: Richard Zhu , Lucas Stach , Frank Li , Sascha Hauer Cc: Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Fabio Estevam , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, rudi@heitbaum.com Subject: [PATCH 0/3] PCI: imx6: select the PCIe REF_CLK source on i.MX8MQ Message-ID: Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-ClientProxiedBy: MEWP282CA0088.AUSP282.PROD.OUTLOOK.COM (2603:10c6:220:1e1::17) To SY7P282MB4909.AUSP282.PROD.OUTLOOK.COM (2603:10c6:10:279::22) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SY7P282MB4909:EE_|SY4P282MB3986:EE_ X-MS-Office365-Filtering-Correlation-Id: c9dce776-5a09-4525-6faa-08def0898866 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|366016|7416014|376014|3023799007|10067099003|5023799004|56012099006|18002099003; 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Commit d8574ce57d76 ("PCI: imx6: Add external reference clock input mode support") added a generic enable_ext_refclk flag, set when an "extref" clock is supplied, and wired it up for i.MX95. This series extends the same mechanism to i.MX8MQ, which resolves the TODO above. Patch 1 allows an optional fifth "extref" clock for fsl,imx8mq-pcie. Patch 2 makes the driver honour enable_ext_refclk on i.MX8MQ. Patch 3 names the oscillator on the in-tree i.MX8MQ boards that have one. Patch 2 must not land before patch 3. On its own it would stop setting REF_USE_PAD on any board that has not declared an "extref" clock, which is all of them today. The reverse order is safe: patch 3 only adds a clock that the driver ignores until patch 2 is applied. Patch 3 touches arch/arm64/boot/dts/freescale and would normally go via the i.MX tree rather than the PCI tree. Given the ordering constraint above, either all three through one tree, or 1 and 3 first with 2 following, would work - whichever the maintainers prefer. Patch 3 is deliberately additive: each board keeps the "pcie_bus" entry it already has and gains a fifth clock naming the same oscillator, so the set of clocks being enabled is unchanged. Tested on a Google Coral Dev Board (imx8mq-phanbell, not yet enabled in mainline), where pcie1 takes the off-chip oscillator and pcie0 the internal PLL. With the extref clock declared, clock-names reads pcie pcie_bus pcie_phy pcie_aux extref pcie1 links at Gen2 and the endpoint enumerates. The five boards touched by patch 3 are untested - I have no access to them. The change is intended to preserve their current behaviour exactly, and review from anyone who has the hardware would be welcome. Rudi Heitbaum (3): dt-bindings: pci: fsl,imx6q-pcie: Add extref clock for i.MX8MQ PCI: imx6: Select the PCIe REF_CLK source on i.MX8MQ arm64: dts: imx8mq: Declare the PCIe extref clock .../devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 8 ++++++-- arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 8 ++++++-- .../boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts | 8 ++++++-- arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts | 4 +++- arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 8 ++++++-- arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 8 ++++++-- drivers/pci/controller/dwc/pci-imx6.c | 9 +++++++-- 7 files changed, 40 insertions(+), 13 deletions(-) -- 2.53.1