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Tue, 22 Sep 2026 05:37:19 -0700 (PDT) Received: from debian.prasanth ([103.183.205.140]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e612ccd46sm6453922eec.18.2026.09.22.05.37.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 05:37:18 -0700 (PDT) From: Prasanth Kumar Padarthi To: joel@jms.id.au Cc: andrew@codeconstruct.com.au, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, ryan_chen@aspeedtech.com, billy_tsai@aspeedtech.com, andrew@lunn.ch, tan.siewert@9elements.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Prasanth Kumar Padarthi Subject: [PATCH v7 0/2] ARM: dts: aspeed: Add ASRock Rack B650D4U BMC support Date: Tue, 22 Sep 2026 18:04:58 +0530 Message-ID: X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add support for the ASRock Rack B650D4U BMC, based on the ASPEED AST2600 SoC. The series adds the board compatible string and describes the BMC memory, SPI NOR flash layout, UART console, GPIO line names, graphics reserved memory, I2C EEPROM, and MAC0 connected to an RTL8211F Ethernet PHY. MAC0 obtains its MAC address from the EEPROM on I2C7 and uses RGMII-ID mode. Changes in v7: * Correct the GPIOP bank line names for the reset, power and NMI button/control signals according to the confirmed board mapping. * Remove the obsolete GPIOF5 reset-button line name. * Leave the binding patch unchanged. The B650D4U DTB builds successfully using aspeed_g5_defconfig. Prasanth Kumar Padarthi (2): dt-bindings: arm: aspeed: Add ASRock Rack B650D4U ARM: dts: aspeed: Add ASRock Rack B650D4U BMC .../bindings/arm/aspeed/aspeed.yaml | 1 + arch/arm/boot/dts/aspeed/Makefile | 1 + .../dts/aspeed/aspeed-bmc-asrock-b650d4u.dts | 135 ++++++++++++++++++ 3 files changed, 137 insertions(+) create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-asrock-b650d4u.dts -- 2.47.3