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Neither mode runs a host tuning sequence (CMD19/CMD21), so the read path must be centred by static, board/SoC-characterised PHY settings. Bringing it up on Agilex5 also exposed PHY issues affecting the existing tuned modes. - Patch 1: settle the PHY once after the final tuning tap, before the first post-tuning command (an R1b CMD6 during HS400 selection can otherwise time out); matches sdhci_cdns6_phy_init(). - Patch 2: program PHONY_DQS_TIMING (left 0 in all modes); in the extended-read DDR modes it must be the rebar pulse width in clk_phy cycles minus 1, else one DDR beat is duplicated. - Patch 3: document three optional SD6HC read-path properties for the extended-read DDR modes (SD DDR50, eMMC DDR52). - Patch 4: read those properties at probe and apply them in DDR50 and DDR52, and make the DQS_TIMING update clear USE_LPBK_DQS before reprogramming it so the loopback/phony selection takes effect. The new cdns,ddr-* properties are unused in this series; they will be consumed by the socfpga_agilex5_socdk and socfpga_agilex5_socdk_emmc device trees, submitted as a separate series. Tested on Agilex5 SoCDK: SD DDR50 and eMMC DDR52. Changes in v2: - Patch 1: moved the 5 ms PHY settle out of the per-tap tuning loop to a single settle after the winning tap, on the success path only, and rewrote the comment to explain this specific call site. (Adrian Hunter, Tanmay Kathpalia) - Patch 2: added Adrian's Acked-by; reworded the commit message to drop the "generic to any SD6HC-PHY SoC" framing. (Adrian Hunter) - Patch 3: retitled to "dt-bindings: mmc: cdns,sd6hc:"; renamed cdns,ddr50-* -> cdns,ddr-*; cdns,ddr-read-dqs-delay-ps is now in picoseconds; replaced the read-DQS source selector with a cdns,ddr-no-lpbk-dqs boolean; reworded the phony-dqs-timing text; dropped the SD4HC note. (Krzysztof Kozlowski, Tanmay Kathpalia) - Patch 4: renamed the properties to cdns,ddr-*; read cdns,ddr-read-dqs-delay-ps in ps and convert it to delay elements (dividing by cdns,delay-element-ps), clamping that quotient to the 8-bit PHY field so a small delay element cannot make it wrap; read cdns,ddr-no-lpbk-dqs via of_property_read_bool() to opt out of the default loopback DQS read path; dropped the v1 per-property range checks and redundant FIELD_MAX() write masks; apply the overrides in both DDR50 and DDR52. Also retitled to "mmc: sdhci-cadence6:" since it touches only the v6 PHY. (Krzysztof Kozlowski, Adrian Hunter, Tanmay Kathpalia) Tze Yee Ng (4): mmc: sdhci-cadence: add PHY settle after tuning for SD6HC mmc: sdhci-cadence6: program PHONY_DQS_TIMING for extended-read DDR dt-bindings: mmc: cdns,sd6hc: add SD6HC DDR50 read-path tuning mmc: sdhci-cadence6: read SD6HC DDR50 tuning from device tree .../devicetree/bindings/mmc/cdns,sd6hc.yaml | 30 ++++++++ drivers/mmc/host/sdhci-cadence-core.c | 6 +- drivers/mmc/host/sdhci-cadence-phy-v6.c | 74 ++++++++++++++++++- 3 files changed, 108 insertions(+), 2 deletions(-) base-commit: 2d2431cf24dda7303d59e47b7d116be8beda66b1 -- 2.43.7