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Mon, 19 Oct 2026 23:32:15 -0700 (PDT) Received: from [192.168.226.26] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c40913c615esm446762566b.42.2026.10.19.23.32.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Oct 2026 23:32:14 -0700 (PDT) Message-ID: Date: Tue, 20 Oct 2026 08:32:10 +0200 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 03/10] clk: qcom: gpucc-msm8998: set the droop detector bit in the right register To: Dmitry Baryshkov , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Joonwoo Park , Imran Khan , Rajendra Nayak , Jeffrey Hugo , Maxime Ripard , Vikash Garodia , Dikshita Agarwal , Bryan O'Donoghue , Mauro Carvalho Chehab , Ilia Lin , Loic Poulain , Konrad Dybcio , Yassine Oudjana , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org References: <20261019-msm8998-fix-clocks-v1-0-370949e4d8a0@oss.qualcomm.com> <20261019-msm8998-fix-clocks-v1-3-370949e4d8a0@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20261019-msm8998-fix-clocks-v1-3-370949e4d8a0@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: Qarz8dqlZyVOaDhNg8f2-FfLTVNcpyl5 X-Proofpoint-ORIG-GUID: Qarz8dqlZyVOaDhNg8f2-FfLTVNcpyl5 X-Authority-Analysis: v=2.4 cv=L7qI0OT8 c=1 sm=1 tr=0 ts=6ad70af0 cx=c_pps a=UgVkIMxJMSkC9lv97toC5g==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=d4jy3kBXdueBcoqUgmMA:9 a=QEXdDO2ut3YA:10 a=1HOtulTD9v-eNWfpl4qZ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIwMDAyNSBTYWx0ZWRfXyW2d6PlpFxc+ 0tkA3qNFWifXHxwcNxiUB/6WdC98o94Yee2nChWtjpwy+3d1gvJfDcqWGzmswjJWDHjOsPmjKbU WZqsLY9l4qSBaCDjmjgb8JXev9Ax83MSQoqgA15KWI/mwuIdv5sDbZhZ4HRIiooCuXiRD668zFo 5rUmQoofjDv/0DefDJyuG3MWK2ju7Y0PSK7oLmuyYdV/WQEQMTM4+IEcBsLRgaCvnu9am1W9wEK Ude/xFvQhhPRGA6U84tKA6DjXc/t2UVSS7lKykClN1chCZkriW0JqvJXxquVWPFs1EIFyx70D9y /elnslaqQv+xK7JOZENksIpdZYCCGnEwjvRKqPEBTJOc3HtYzVBcdhCqhZ67VY6rsXBwe4vx2rw f0or2l+b89KHVnHsVpyUtabcq6MpLJ/vVZtOeIpNMm138/3qGie2AP5BFh5iqsvXRmMSIhcpRPD J+pgXdAqVViRC01aszQ== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIwMDAyNSBTYWx0ZWRfX15alSvyHtuMo Iaan/81vzccIeG+Y7y9j4X5EXNKcattY8Ln55b8y7XCNt0Ep026fhQz4aNrhCOJHfH2yyxYUJrc uAeGtYslM+hrrnAdJ6ct9Etul07rjh4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-20_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 suspectscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610200025 On 10/19/26 3:41 PM, Dmitry Baryshkov wrote: > The probe means to power down the GPU droop detector to cut the leakage > between the graphics and CX rails, but it sets bit 0 of the GFX3D branch > register instead of GPUCC_GPU_DD_WRAP_CTRL. That force-enables the GFX3D > clock and leaves the droop detector alone. > > Write the bit to GPUCC_GPU_DD_WRAP_CTRL, as the vendor driver does. > > Fixes: 3f7df5baa259 ("clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver") > Signed-off-by: Dmitry Baryshkov > --- > drivers/clk/qcom/gpucc-msm8998.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c > index 066793e47f79..8da10027f1f2 100644 > --- a/drivers/clk/qcom/gpucc-msm8998.c > +++ b/drivers/clk/qcom/gpucc-msm8998.c > @@ -330,7 +330,7 @@ static int gpucc_msm8998_probe(struct platform_device *pdev) > /* force periph logic on to avoid perf counter corruption */ > regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(13), BIT(13)); > /* tweak droop detector (GPUCC_GPU_DD_WRAP_CTRL) to reduce leakage */ > - regmap_write_bits(regmap, gfx3d_clk.clkr.enable_reg, BIT(0), BIT(0)); > + regmap_write_bits(regmap, 0x430, BIT(0), BIT(0)); regmap_set_bits(), would also be nice if this was moved to the new driver_data. with or without that: Reviewed-by: Konrad Dybcio Konrad