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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dc09fc2d9sm3167994f8f.6.2025.02.07.00.13.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Feb 2025 00:13:57 -0800 (PST) Message-ID: Date: Fri, 7 Feb 2025 09:13:56 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 09/21] RISC-V: Add Ssccfg ISA extension definition and parsing To: Atish Patra , Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> <20250205-counter_delegation-v4-9-835cfa88e3b1@rivosinc.com> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: <20250205-counter_delegation-v4-9-835cfa88e3b1@rivosinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 06/02/2025 08:23, Atish Patra wrote: > Ssccfg (‘Ss’ for Privileged architecture and Supervisor-level > extension, ‘ccfg’ for Counter Configuration) provides access to > delegated counters and new supervisor-level state. > > This patch just enables the definitions and enable parsing. > > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/hwcap.h | 2 ++ > arch/riscv/kernel/cpufeature.c | 2 ++ > 2 files changed, 4 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index b4eddcb57842..fa5e01bcb990 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -103,6 +103,8 @@ > #define RISCV_ISA_EXT_SSCSRIND 94 > #define RISCV_ISA_EXT_SMCSRIND 95 > #define RISCV_ISA_EXT_SMCNTRPMF 96 > +#define RISCV_ISA_EXT_SSCCFG 97 > +#define RISCV_ISA_EXT_SMCDELEG 98 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 8f225c9c3055..3cb208d4913e 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -390,12 +390,14 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), > __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > + __RISCV_ISA_EXT_DATA(smcdeleg, RISCV_ISA_EXT_SMCDELEG), Hi Atish, based on your dt-binding commit, if smcdeleg depends on Sscsrind, Zihpm, Zicntr, then you could add a validation callback here: static int riscv_smcdeleg_validate(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_SSCSRIND) && __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZIHPM) && __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZICNTR)) return 0; return -EPROBE_DEFER; } __RISCV_ISA_EXT_DATA_VALIDATE(smcdeleg, RISCV_ISA_EXT_SMCDELEG, riscv_smcdeleg_validate), > __RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF), > __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), > __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), > __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts), > __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), > __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > + __RISCV_ISA_EXT_DATA(ssccfg, RISCV_ISA_EXT_SSCCFG), Ditto for this one with Smcdeleg, Sscsrind, Zihpm, Zicntr, Sscofpmf, Smcntrpmf. Thanks, Clément > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > __RISCV_ISA_EXT_DATA(sscsrind, RISCV_ISA_EXT_SSCSRIND), > __RISCV_ISA_EXT_SUPERSET(ssnpm, RISCV_ISA_EXT_SSNPM, riscv_xlinuxenvcfg_exts), >