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Wed, 08 Oct 2025 05:47:56 -0700 (PDT) Message-ID: Date: Wed, 8 Oct 2025 15:47:55 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 4/7] reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY From: Claudiu Beznea To: Philipp Zabel , vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, yoshihiro.shimoda.uh@renesas.com, biju.das.jz@bp.renesas.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Claudiu Beznea , Wolfram Sang References: <20250925100302.3508038-1-claudiu.beznea.uj@bp.renesas.com> <20250925100302.3508038-5-claudiu.beznea.uj@bp.renesas.com> <66d85e70-efb8-4a45-9164-55b123691b70@tuxon.dev> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/8/25 15:16, Claudiu Beznea wrote: > Hi, Philipp, > > On 10/8/25 13:23, Philipp Zabel wrote: >> Hi Claudiu, >> >> On Mi, 2025-10-08 at 12:29 +0300, Claudiu Beznea wrote: >>> Hi, Philipp, >>> >>> On 10/8/25 11:34, Philipp Zabel wrote: >>>> Hi Claudiu, >>>> >>>> On Do, 2025-09-25 at 13:02 +0300, Claudiu wrote: >>>>> From: Claudiu Beznea >>>>> >>>>> On the Renesas RZ/G3S SoC, the USB PHY block has an input signal called >>>>> PWRRDY. This signal is managed by the system controller and must be >>>>> de-asserted after powering on the area where USB PHY resides and asserted >>>>> before powering it off. >>>>> >>>>> On power-on the USB PWRRDY signal need to be de-asserted before enabling >>>>> clock and switching the module to normal state (through MSTOP support). The >>>>> power-on configuration sequence >>>> >>>> The wording makes me wonder, have you considered implementing this as a >>>> power sequencing driver? >>> >>> No, haven't tried as power sequencing. At the moment this was started I >>> think the power sequencing support wasn't merged. >>> >>> The approaches considered were: >>> a/ power domain >> >> Letting a power domain control a corresponding power ready signal would >> have been my first instinct as well. >> >>> b/ regulator >>> c/ as a reference counted bit done through regmap read/writes APIs >>> >>> a and b failed as a result of discussions in the previous posted versions. >> >> Could you point me to the discussion related to a? > > It's this one > https://lore.kernel.org/all/CAPDyKFrS4Dhd7DZa2zz=oPro1TiTJFix0awzzzp8Qatm-8Z2Ug@mail.gmail.com/ > > >> >> I see v2 and v3 tried to control the bit from the PHY drivers, and in >> v4 we were are already back to the reset driver. > > v2 passed the system controller (SYSC) phandle to the USB PHYs only (though > renesas,sysc-signals DT property) where the PWRRDY bit was set. The PWRRDY > bit was referenced counted in the SYSC driver though regmap APIs. Sorry, I forgot to mention: in v2, the SYSC phandle was passed to the PHYs only as I wasn't aware of the block diagram presented in this patch description. I got aware of the block diagram starting with v3. Thank you, Claudiu