From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 039CBAD31; Thu, 21 Dec 2023 04:36:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PudtbnkL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5EA1DC433C8; Thu, 21 Dec 2023 04:36:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1703133385; bh=Ye0z8hSnZkvGRVITl2wlNpanlqLTvzdlfbhdatzGoR4=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=PudtbnkLI0SC9Z0NDsUUSzMU0ipAjqo60oSzraQ7xsNN3sdgdBZAAUxAiLxBLQcxm C3r9vtGIiK4fwmrQce1zVRLHaZD+6R1nASG367QBQV0YIgHS10p7UUpjKFcOP9fhuV M0dPvCvdsLHf3kD/dx9weNUjr8R575aiZvYX27vMePLLepvRuWwrXz6BsR6fDcHTll Lanq0JZV+JeXdzeAQRndBdLNx2P02z2ViR6g1fozSAe30hXvqka96EGodMSbJzaWYM P+2XObkg0V6nk0JfnilGyuUV2PZLi6oaBTdKjRsZL59k89Nbsgf1GWNO+sYPOdVqPA lHZkPIkJ7EDtQ== Message-ID: Content-Type: text/plain; charset="utf-8" Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20231220-sa8295p-gpu-v1-2-d8cdf2257f97@quicinc.com> References: <20231220-sa8295p-gpu-v1-0-d8cdf2257f97@quicinc.com> <20231220-sa8295p-gpu-v1-2-d8cdf2257f97@quicinc.com> Subject: Re: [PATCH 2/8] clk: qcom: gdsc: Enable supply reglator in GPU GX handler From: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Bjorn Andersson To: Bjorn Andersson , Bjorn Andersson , Catalin Marinas , Conor Dooley , Johan Hovold , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Rob Herring , Taniya Das , Ulf Hansson , Will Deacon Date: Wed, 20 Dec 2023 20:36:23 -0800 User-Agent: alot/0.10 Quoting Bjorn Andersson (2023-12-20 19:50:36) > The GX GDSC is modelled to aid the GMU in powering down the GPU in the > event that the GPU crashes, so that it can be restarted again. But in > the event that the power-domain is supplied through a dedicated > regulator (in contrast to being a subdomin of another power-domain), > something needs to turn that regulator on, both to make sure things are > powered and to match the operation in gdsc_disable(). >=20 > Signed-off-by: Bjorn Andersson > --- > drivers/clk/qcom/gdsc.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c > index 5358e28122ab..d1139c895503 100644 > --- a/drivers/clk/qcom/gdsc.c > +++ b/drivers/clk/qcom/gdsc.c > @@ -557,7 +557,13 @@ void gdsc_unregister(struct gdsc_desc *desc) > */ > int gdsc_gx_do_nothing_enable(struct generic_pm_domain *domain) > { > + struct gdsc *sc =3D domain_to_gdsc(domain); > + int ret =3D 0; > + > /* Do nothing but give genpd the impression that we were successf= ul */ Update this comment. > - return 0; > + if (sc->rsupply) > + ret =3D regulator_enable(sc->rsupply); > + > + return ret; > }