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([2a00:f41:900a:a4b1:9ab2:4d92:821a:bb76]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ca2872466sm284108e87.143.2024.06.13.09.58.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Jun 2024 09:58:36 -0700 (PDT) Message-ID: Date: Thu, 13 Jun 2024 18:58:33 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V4 1/8] clk: qcom: clk-alpha-pll: Fix CAL_L_VAL override for LUCID EVO PLL To: Ajit Pandey , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Vinod Koul , Vladimir Zapolskiy Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Jagadeesh Kona , Imran Shaik , Satya Priya Kakitapalli , stable@vger.kernel.org, Dmitry Baryshkov References: <20240611133752.2192401-1-quic_ajipan@quicinc.com> <20240611133752.2192401-2-quic_ajipan@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20240611133752.2192401-2-quic_ajipan@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/11/24 15:37, Ajit Pandey wrote: > In LUCID EVO PLL CAL_L_VAL and L_VAL bitfields are part of single > PLL_L_VAL register. Update for L_VAL bitfield values in PLL_L_VAL > register using regmap_write() API in __alpha_pll_trion_set_rate > callback will override LUCID EVO PLL initial configuration related > to PLL_CAL_L_VAL bit fields in PLL_L_VAL register. > > Observed random PLL lock failures during PLL enable due to such > override in PLL calibration value. Use regmap_update_bits() with > L_VAL bitfield mask instead of regmap_write() API to update only > PLL_L_VAL bitfields in __alpha_pll_trion_set_rate callback. > > Fixes: 260e36606a03 ("clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces") > Cc: stable@vger.kernel.org > Signed-off-by: Ajit Pandey > Reviewed-by: Dmitry Baryshkov > --- > drivers/clk/qcom/clk-alpha-pll.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c > index c51647e37df8..a538559caaa0 100644 > --- a/drivers/clk/qcom/clk-alpha-pll.c > +++ b/drivers/clk/qcom/clk-alpha-pll.c > @@ -1665,7 +1665,7 @@ static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, > if (ret < 0) > return ret; > > - regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); > + regmap_update_bits(pll->clkr.regmap, PLL_L_VAL(pll), LUCID_EVO_PLL_L_VAL_MASK, l); Since you're altering a function used by LUCID and TRION PLLs.. how will that affect non-LUCID_EVO/OLE ones? Konrad