From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7D0E15886D; Thu, 24 Oct 2024 09:46:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729763161; cv=none; b=KZy6uFHN3E4O0vyklEvUD+sNV8v7TIORwmCcHWFAA2vKYRzDPC57wcD+XXCB686AiesPKZQsJiR0MD8In8zRoC3USu345y6yI1I3CpB5jtktxlr4mzCIIhmq6E60pvQhgRPMTLkUj95ycMNPWCaOIVHXNga5lh6c20guiEsdmcA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729763161; c=relaxed/simple; bh=TP20U8M2gkMXngG5jt8yo0o5myFCfbGLJyktlLYRLxE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=lsWsQi7A4f+8XVHKwvrrtRoLiX1aZhFxnoHMrDJ3bTAdtf9v6+QLwnHCHPyjGku22hZfO9rSMDW5UfGysflryaslEhN9kJF9iU6fAGUEtrRC5bli0LICXNuSV/aW47YoM0h4jEeMkmqjcKfjHi3BGlKzS6aPE3KPNCgDKLyKWoM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nMB4oMO5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nMB4oMO5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 199C8C4CECC; Thu, 24 Oct 2024 09:45:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729763161; bh=TP20U8M2gkMXngG5jt8yo0o5myFCfbGLJyktlLYRLxE=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=nMB4oMO5FoeZ4p/LGdZ2lPbtjU5xPPsN3KJwkC0MLrR5sq8z2LkktpgmETu+logty 7GijuQcd0H0U/78gM/myotb56r8FN02IiSc5LW4Nf4mAvry78k9Vr5RQx2aLvjFF5J 51C8eeJFIWig6dQixaMrBWlLQbW7EDpLG48ilXUv+cEVCI3azduXCYv2xTcJdFo4CR KiMH5A8zOqRwhOxYKh+LH/twQNWPnaGtzmNpeOQnCiyNtId8MR25BrhhtbMKnWWIiz clzm1vlY4dQ9sjh/mYDeUgeYMMCTfCz9araohAyeFokTgj+09tStr7aq+EfcsGscPR Y30Tz1IKbvD4Q== Message-ID: Date: Thu, 24 Oct 2024 11:45:53 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] mailbox: mediatek: Add mtk-apu-mailbox driver To: "Karl.Li" , Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Chungying Lu , Project_Global_Chrome_Upstream_Group@mediatek.com References: <20241024092608.431581-1-karl.li@mediatek.com> <20241024092608.431581-4-karl.li@mediatek.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 24/10/2024 11:25, Karl.Li wrote: > From: Karl Li > > Add mtk-apu-mailbox driver to support the communication with > APU remote microprocessor. > > Also, the mailbox hardware contains extra spare (scratch) registers > that other hardware blocks use to communicate through. > Expose these with custom mtk_apu_mbox_(read|write)() functions. > > Signed-off-by: Karl Li > --- > drivers/mailbox/Kconfig | 9 + > drivers/mailbox/Makefile | 2 + > drivers/mailbox/mtk-apu-mailbox.c | 222 ++++++++++++++++++++++++ > include/linux/mailbox/mtk-apu-mailbox.h | 20 +++ > 4 files changed, 253 insertions(+) > create mode 100644 drivers/mailbox/mtk-apu-mailbox.c > create mode 100644 include/linux/mailbox/mtk-apu-mailbox.h > > diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig > index 6fb995778636..2338e08a110a 100644 > --- a/drivers/mailbox/Kconfig > +++ b/drivers/mailbox/Kconfig > @@ -240,6 +240,15 @@ config MTK_ADSP_MBOX > between processors with ADSP. It will place the message to share > buffer and will access the ipc control. > > +config MTK_APU_MBOX > + tristate "MediaTek APU Mailbox Support" > + depends on ARCH_MEDIATEK || COMPILE_TEST > + help > + Say yes here to add support for the MediaTek APU Mailbox > + driver. The mailbox implementation provides access from the > + application processor to the MediaTek AI Processing Unit. > + If unsure say N. > + > config MTK_CMDQ_MBOX > tristate "MediaTek CMDQ Mailbox Support" > depends on ARCH_MEDIATEK || COMPILE_TEST > diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile > index 3c3c27d54c13..6b6dcc78d644 100644 > --- a/drivers/mailbox/Makefile > +++ b/drivers/mailbox/Makefile > @@ -53,6 +53,8 @@ obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o > > obj-$(CONFIG_MTK_ADSP_MBOX) += mtk-adsp-mailbox.o > > +obj-$(CONFIG_MTK_APU_MBOX) += mtk-apu-mailbox.o > + > obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o > > obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o > diff --git a/drivers/mailbox/mtk-apu-mailbox.c b/drivers/mailbox/mtk-apu-mailbox.c > new file mode 100644 > index 000000000000..b347ebd34ef7 > --- /dev/null > +++ b/drivers/mailbox/mtk-apu-mailbox.c > @@ -0,0 +1,222 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2024 MediaTek Inc. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define INBOX (0x0) > +#define OUTBOX (0x20) > +#define INBOX_IRQ (0xc0) > +#define OUTBOX_IRQ (0xc4) > +#define INBOX_IRQ_MASK (0xd0) > + > +#define SPARE_OFF_START (0x40) > +#define SPARE_OFF_END (0xB0) > + > +struct mtk_apu_mailbox { > + struct device *dev; > + void __iomem *regs; > + struct mbox_controller controller; > + u32 msgs[MSG_MBOX_SLOTS]; > +}; > + > +struct mtk_apu_mailbox *g_mbox; Why this is global? And why do you support only one device? No, drop. > + > +static irqreturn_t mtk_apu_mailbox_irq_top_half(int irq, void *dev_id) > +{ > + struct mtk_apu_mailbox *mbox = dev_id; > + struct mbox_chan *link = &mbox->controller.chans[0]; > + int i; > + > + for (i = 0; i < MSG_MBOX_SLOTS; i++) > + mbox->msgs[i] = readl(mbox->regs + OUTBOX + i * sizeof(u32)); > + > + mbox_chan_received_data(link, &mbox->msgs); > + > + return IRQ_WAKE_THREAD; > +} > + ... > +/** > + * mtk_apu_mbox_write - Write value to specifice mtk_apu_mbox spare register. > + * @val: Value to be written. > + * @offset: Offset of the spare register. > + * > + * Return: 0 if successful > + * negative value if error happened > + */ > +int mtk_apu_mbox_write(u32 val, u32 offset) > +{ > + if (!g_mbox) { > + pr_err("mtk apu mbox was not initialized, stop writing register\n"); > + return -ENODEV; > + } > + > + if (offset < SPARE_OFF_START || offset >= SPARE_OFF_END) { > + dev_err(g_mbox->dev, "Invalid offset %d for mtk apu mbox spare register\n", offset); > + return -EINVAL; > + } > + > + writel(val, g_mbox->regs + offset); > + return 0; > +} > +EXPORT_SYMBOL_NS(mtk_apu_mbox_write, MTK_APU_MAILBOX); Use mailbox API. This is really poor solution. > + > +/** > + * mtk_apu_mbox_read - Read value to specifice mtk_apu_mbox spare register. > + * @offset: Offset of the spare register. > + * @val: Pointer to store read value. > + * > + * Return: 0 if successful > + * negative value if error happened > + */ > +int mtk_apu_mbox_read(u32 offset, u32 *val) > +{ > + if (!g_mbox) { > + pr_err("mtk apu mbox was not initialized, stop reading register\n"); > + return -ENODEV; > + } > + > + if (offset < SPARE_OFF_START || offset >= SPARE_OFF_END) { > + dev_err(g_mbox->dev, "Invalid offset %d for mtk apu mbox spare register\n", offset); > + return -EINVAL; > + } > + > + *val = readl(g_mbox->regs + offset); > + > + return 0; > +} > +EXPORT_SYMBOL_NS(mtk_apu_mbox_read, MTK_APU_MAILBOX); > + > +static int mtk_apu_mailbox_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mtk_apu_mailbox *mbox; > + int irq = -1, ret = 0; > + > + mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL); > + if (!mbox) > + return -ENOMEM; > + > + mbox->dev = dev; > + platform_set_drvdata(pdev, mbox); > + > + mbox->regs = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(mbox->regs)) > + return PTR_ERR(mbox->regs); > + > + mbox->controller.txdone_irq = false; > + mbox->controller.txdone_poll = true; > + mbox->controller.txpoll_period = 1; > + mbox->controller.ops = &mtk_apu_mailbox_ops; > + mbox->controller.dev = dev; > + /* > + * Here we only register 1 mbox channel. > + * The remaining channels are used by other modules. > + */ > + mbox->controller.num_chans = 1; > + mbox->controller.chans = devm_kcalloc(dev, mbox->controller.num_chans, > + sizeof(*mbox->controller.chans), > + GFP_KERNEL); > + if (!mbox->controller.chans) > + return -ENOMEM; > + > + ret = devm_mbox_controller_register(dev, &mbox->controller); > + if (ret) > + return ret; > + > + irq = platform_get_irq(pdev, 0); > + if (irq < 0) > + return irq; > + > + ret = devm_request_threaded_irq(dev, irq, mtk_apu_mailbox_irq_top_half, > + mtk_apu_mailbox_irq_btm_half, IRQF_ONESHOT, > + dev_name(dev), mbox); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to request IRQ\n"); > + > + g_mbox = mbox; > + > + dev_dbg(dev, "registered mtk apu mailbox\n"); No, drop such stuff. > + > + return 0; > +} > + > +static void mtk_apu_mailbox_remove(struct platform_device *pdev) > +{ > + g_mbox = NULL; > +} > + > +static const struct of_device_id mtk_apu_mailbox_of_match[] = { > + { .compatible = "mediatek,mt8188-apu-mailbox" }, > + { .compatible = "mediatek,mt8196-apu-mailbox" }, So devices are compatible? Make them compatible in the binding and drop unneeded compatible here. Best regards, Krzysztof