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Wed, 21 Oct 2026 08:52:26 -0700 (PDT) Received: from [192.168.1.10] ([122.164.81.208]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3674198f1cdsm9445801eec.25.2026.10.21.08.52.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 21 Oct 2026 08:52:25 -0700 (PDT) Message-ID: Date: Wed, 21 Oct 2026 21:22:18 +0530 X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] dt-bindings: clock: ipq9650-apss-clk: Add IPQ9650 apss clock controller To: Krzysztof Kozlowski Cc: Georgi Djakov , Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20261007-ipq9650_apss_clk-v1-0-fd4c2b3cbdea@oss.qualcomm.com> <20261007-ipq9650_apss_clk-v1-3-fd4c2b3cbdea@oss.qualcomm.com> <20261013-quantum-keen-mongrel-c3736c@quoll> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: <20261013-quantum-keen-mongrel-c3736c@quoll> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=d4JgWhjE c=1 sm=1 tr=0 ts=6ad8dfbb cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=rZLzW5DhxuwyX7/NBrPT8g==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=mdBYyscGZtZr9QMU3J0A:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA2MyBTYWx0ZWRfX7ds0VcIVwQul qJuki1fdehI91/y0VRfYpCauXW6w1abw0PuGPQR1TEkybn97UbAdeMRDcAGuS9wAQRcFdDpr0ZL miJn1wICrtsVDKL8xGEnWx3Jkegqh+c= X-Proofpoint-GUID: 7EJfDT0PrdxMs7Mizogwjr9IHUyB4cOF X-Proofpoint-ORIG-GUID: 7EJfDT0PrdxMs7Mizogwjr9IHUyB4cOF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA2MyBTYWx0ZWRfXy6f3V8rAJMFx KIp0RA40wGdCwPlt+HCpNQFNA+zKfopyKrcyRD/bd/ixWjceTBpqJY8Y58MWKNrAseQMZduzuKp O2192Gqw/eoPzwhN73zVhUeSRN63INQ+4wSVD6WyDUP+0VxeucdyK6IJsiyAHSUQYrkytJ2MmhX ZE2Ln42C4eDwShLDlb1P98RcEYkpNCqcGgkbZ1vfwzvZ/7c7cBO4JNVkhiFhDBbqQbRpBn/8beh dd4A93+bRG+ANCCT+YXWwi3RUDCldy480dZ/V1dXtd7QK6XVaFDDLQseb/JnYhDzXd8SCWMK3Wv Js68FHTLIlM/6/fRtDAwTJxu3hsMMqe1eDfVHAO3tu7yj0w3UA0w614IuasXM2JIFo60EdM3gqn BLw1wnEzoYZM+zF36wyXzH3PLKkPeJ1JxqA/uZEqUYKjSeaQXlKEWmd5wHCjpoE9LO+sfLr1roD mgKJzUuORgAecrpc22A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_04,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 suspectscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210063 On 10/13/2026 12:17 PM, Krzysztof Kozlowski wrote: > On Wed, Oct 07, 2026 at 12:20:46PM +0530, Kathiravan Thirumoorthy wrote: >> The APSS clock controller on IPQ9650 provides the CPU and L3 clocks and >> has a register space separate from the GCC. The four Cortex-A55 cores, >> the Cortex-A78 core and the L3 are each clocked by their own Zonda PLL, >> selected through a glitch-free mux whose parents are XO, GPLL0 and the >> corresponding PLL. The L3 needs to be scaled along with the CPUs, so the >> controller is also an interconnect provider. >> >> Add the binding, the clock indices for the Cortex-A78 (gold) cluster to >> the shared APSS header, and the interconnect IDs for the CPU and L3 >> nodes. >> >> Signed-off-by: Kathiravan Thirumoorthy >> --- >> .../bindings/clock/qcom,ipq9650-apss-clk.yaml | 58 ++++++++++++++++++++++ >> include/dt-bindings/clock/qcom,apss-ipq.h | 5 ++ >> include/dt-bindings/interconnect/qcom,ipq9650.h | 4 ++ >> 3 files changed, 67 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9650-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9650-apss-clk.yaml >> new file mode 100644 >> index 000000000000..6b47183edd56 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9650-apss-clk.yaml >> @@ -0,0 +1,58 @@ >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/clock/qcom,ipq9650-apss-clk.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm APSS IPQ9650 Clock Controller >> + >> +maintainers: >> + - Kathiravan Thirumoorthy >> + >> +description: >> + The APSS clock controller provides the CPU and L3 clocks on IPQ9650 and >> + has a register space separate from the GCC. The four Cortex-A55 cores, >> + the Cortex-A78 core and the L3 are each clocked by their own Zonda PLL. >> + Each clock is selected through a glitch-free mux (GFM) whose parents are >> + XO, GPLL0 and the corresponding PLL. >> + >> +properties: >> + compatible: >> + enum: >> + - qcom,ipq9650-apss-clk >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: Reference to the XO clock. >> + - description: Reference to the GPLL0 clock. > Why do you need a new file? Looks exactly the same as existing > ipq5424-apss-clk. I kept it separate because the IPQ9650 block uses a GFM instead of an RCG, but that's internal to the controller and the compatible covers it. The binding interface is the same, so I'll add qcom,ipq9650-apss-clk to qcom,ipq5424-apss-clk.yaml in v2. > > > Best regards, > Krzysztof >