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Tue, 9 May 2023 15:26:18 +0000 Received: from DB9PR03MB8847.eurprd03.prod.outlook.com ([fe80::d632:8122:75f7:7b0e]) by DB9PR03MB8847.eurprd03.prod.outlook.com ([fe80::d632:8122:75f7:7b0e%3]) with mapi id 15.20.6363.033; Tue, 9 May 2023 15:26:18 +0000 Message-ID: Date: Tue, 9 May 2023 11:26:12 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: [PATCH v14 06/15] clk: Add Lynx 10G SerDes PLL driver Content-Language: en-US To: Vinod Koul Cc: Kishon Vijay Abraham I , linux-phy@lists.infradead.org, Madalin Bucur , linux-arm-kernel@lists.infradead.org, Camelia Alexandra Groza , devicetree@vger.kernel.org, Rob Herring , linuxppc-dev@lists.ozlabs.org, Bagas Sanjaya , Krzysztof Kozlowski , Ioana Ciornei , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org References: <20230413160607.4128315-1-sean.anderson@seco.com> <20230413160607.4128315-7-sean.anderson@seco.com> <1012f955-180e-0013-cc13-1da10991b5f5@seco.com> From: Sean Anderson In-Reply-To: Content-Type: text/plain; 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X-OriginatorOrg: seco.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2023 15:26:24.6292 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 65119b38-35b3-476e-40ae-08db50a1c02b X-MS-Exchange-CrossTenant-Id: bebe97c3-6438-442e-ade3-ff17aa50e733 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=bebe97c3-6438-442e-ade3-ff17aa50e733;Ip=[20.160.56.85];Helo=[inpost-eu.tmcas.trendmicro.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR05FT034.eop-eur05.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR03MB6990 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 5/9/23 09:00, Vinod Koul wrote: > On 08-05-23, 11:31, Sean Anderson wrote: >> On 5/8/23 05:15, Vinod Koul wrote: > >> >> +int lynx_clks_init(struct device *dev, struct regmap *regmap, >> >> + struct clk *plls[2], struct clk *ex_dlys[2], bool compat); >> > >> > so you have an exported symbol for clk driver init in phy driver header? >> > can you please explain why..? >> >> So that it can be called at the appropriate time during the phy's probe function. >> >> This is really an integral part of the phy driver, but I was directed to split it >> off and put it in another subsystem's directory. > > That is right clock should be belong to clk driver. IIUC the hardware is > phy along with clocks and you are doing the clk init. I think that may > not be correct model, you should really have a device tree node to > represent the clock and the phy node > > > What stops this from being modelled as it is in the hardware? It *is* modeled as it is in hardware. With just the serdes compatible, we have all the information we need to create the clocks. So we do so. There's no need for a separate device just to create four clocks. These clocks cannot be used by any other device (except possibly by putting a lane into test mode). So there is no benefit from making them a separate device, except an increase in complexity due to ordering and dynamic lookup. By doing things this way we know that either there was an error or the clocks all exist, and the lifetime of the clocks matches the serdes. --Sean