From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Frank Li <Frank.Li@nxp.com>,
tglx@linutronix.de, maz@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kw@linux.com, bhelgaas@google.com,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org,
peng.fan@nxp.com, aisheng.dong@nxp.com, jdmason@kudzu.us
Cc: kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
kishon@ti.com, lorenzo.pieralisi@arm.com, ntb@lists.linux.dev
Subject: Re: [PATCH 2/3] dt-bindings: irqchip: imx mu work as msi controller
Date: Tue, 12 Jul 2022 12:25:54 +0200 [thread overview]
Message-ID: <d28ea0ac-ff1b-5394-4c76-1561353ab7ce@linaro.org> (raw)
In-Reply-To: <20220707210238.917477-2-Frank.Li@nxp.com>
On 07/07/2022 23:02, Frank Li wrote:
> imx mu support generate irq by write a register.
> provide msi controller support so other driver
> can use it by standard msi interface.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> .../interrupt-controller/fsl,mu-msi.yaml | 94 +++++++++++++++++++
> 1 file changed, 94 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml
> new file mode 100644
> index 0000000000000..b4ac583f60227
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX Messaging Unit (MU)
> +
> +maintainers:
> + - Frank Li <Frank.Li@nxp.com>
> +
> +description: |
> + The Messaging Unit module enables two processors within the SoC to
> + communicate and coordinate by passing messages (e.g. data, status
> + and control) through the MU interface. The MU also provides the ability
> + for one processor to signal the other processor using interrupts.
> +
> + Because the MU manages the messaging between processors, the MU uses
> + different clocks (from each side of the different peripheral buses).
> + Therefore, the MU must synchronize the accesses from one side to the
> + other. The MU accomplishes synchronization using two sets of matching
> + registers (Processor A-facing, Processor B-facing).
> +
> + MU can work as msi interrupt controller to do doorbell
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: fsl,imx6sx-mu-msi
> + - const: fsl,imx7ulp-mu-msi
> + - const: fsl,imx8ulp-mu-msi
> + - const: fsl,imx8-mu-msi
> + - const: fsl,imx8ulp-mu-msi-s4
Use enum
> + - items:
> + - const: fsl,imx8ulp-mu-msi
Single item... why?
> + - items:
> + - enum:
> + - fsl,imx7s-mu-msi
> + - fsl,imx8mq-mu-msi
> + - fsl,imx8mm-mu-msi
> + - fsl,imx8mn-mu-msi
> + - fsl,imx8mp-mu-msi
> + - fsl,imx8qm-mu-msi
Why qm is here not compatible with qxp? It's already mentioned in
section below.
> + - fsl,imx8qxp-mu-msi
> + - const: fsl,imx6sx-mu-msi
> + - description: MU work as msi controller
> + items:
> + - enum:
> + - fsl,imx8qm-mu-msi
> + - fsl,imx8qxp-mu-msi
> + - const: fsl,imx6sx-mu-msi
> + reg:
> + maxItems: 2
> +
> + interrupts:
> + minItems: 1
> + maxItems: 2
Instead describe the items.
> +
> + interrupt-names:
> + minItems: 1
> + items:
> + - const: tx
> + - const: rx
> +
> + clocks:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - msi-controller
How this end up here?
Aren't you missing allOf with a reference to msi-controller?
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + lsio_mu12: msi@5d270000 {
> + compatible = "fsl,imx6sx-mu-msi-db";
???
> + msi-controller;
> + interrupt-controller;
??? How this appeared here
Also fix your indentation like in example-schema.
> + reg = <0x5d270000 0x10000>, /* A side */
> + <0x5d300000 0x10000>; /* B side */
> + reg-names = "a", "b";
> + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&pd IMX_SC_R_MU_12A>,
> + <&pd IMX_SC_R_MU_12B>;
Please do not send untested bindings. It's a waste of our time.
Really two items here? You just said only one is allowed.
> + power-domain-names = "a", "b";
Sorry, this patch looks really poor. a/b is not a descriptive name and
they are not allowed by your own bindings. Please perform some internal
reviews...
> + };
Best regards,
Krzysztof
next prev parent reply other threads:[~2022-07-12 10:26 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-07 21:02 [PATCH 1/3] irqchip: imx mu worked as msi controller Frank Li
2022-07-07 21:02 ` [PATCH 2/3] dt-bindings: irqchip: imx mu work " Frank Li
2022-07-08 21:32 ` Rob Herring
2022-07-12 10:25 ` Krzysztof Kozlowski [this message]
2022-07-15 19:35 ` [EXT] " Frank Li
2022-07-07 21:02 ` [PATCH 3/3] pcie: endpoint: pci-epf-vntb: add endpoint msi support Frank Li
2022-07-08 8:01 ` [PATCH 1/3] irqchip: imx mu worked as msi controller Marc Zyngier
2022-07-08 8:58 ` Marc Zyngier
2022-07-08 16:26 ` [EXT] " Frank Li
2022-07-09 8:16 ` Marc Zyngier
2022-07-09 15:23 ` Frank Li
2022-07-13 18:28 ` Frank Li
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