From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EB0D2E6116; Mon, 18 May 2026 07:07:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779088047; cv=none; b=aptIBBw6FwEcsmqdEuE+Qg7MVuZrk0TwuvDQanJaoagxcOyaEat1kty4AWI8qzgZT1S51BU+tLhqceo3d52KONvdjbmh7SDwRomkvp9uPy4+xKkYVUpPHxE3ZCVWFm/N2mMxy1eCKvNeT29AHX61qM1VOftsh4tGqD3b0Y8/rw8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779088047; c=relaxed/simple; bh=MKXLogmGk/Z9aRPLYSGv52Z8vYljivWCzlY49r4KzWA=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=NBPJt13okboEzsDC2cqTa18Wv3JILewNnc3pA0zLgivOOXhJIHtW5hCPrkw0ZeglfC+XfwabkeDGawQ6sIqDUmoB5Q7zZcgx160wAhPIWY2dHPC6fLGDBGJZq82t2gg+8vdH9dyilQWabnzoSN+MltrlvlL8tme02Cd+GRgSVLg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Yr1pcdAR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Yr1pcdAR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AA450C2BCB7; Mon, 18 May 2026 07:07:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1779088046; bh=MKXLogmGk/Z9aRPLYSGv52Z8vYljivWCzlY49r4KzWA=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=Yr1pcdARntEinFCi3Pgr8QrJfRwlIgARnLjU9Bqebhq5KT1/3hpKCyxL6VPLRPBSY LncYEHPlcDmCoRR/SSHrZ4ul8lHROTdUsWkvbltZIbeOPGTgiawxTdd54hjiIXZVMA b3+uWzfy+HPMKzcwNIjYlHOb0+QzQdcg3uV+oNSpFpaYgVx2dd4Hl5+aowGq5J/+b6 MFs3MDevHEtoGqIYV4z2UalIn1TDGSno562eKaxalkn8nLriagOXed6P14NVqdC6+c qw36E0nsAz7eF7CkNxDz1trpoGc0HK6L5Zpt0p8srr51XGgPesZUUpi8Y+B8qnXKl8 t15ThCvxxvbDw== Message-ID: Date: Mon, 18 May 2026 09:07:21 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/5] dt-bindings: connector: Add fsl,io-connector binding To: Chancel Liu Cc: "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , Frank Li , "s.hauer@pengutronix.de" , "festevam@gmail.com" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "kernel@pengutronix.de" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "imx@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , "linux-clk@vger.kernel.org" References: <20260509024846.2094049-1-chancel.liu@nxp.com> <20260509024846.2094049-3-chancel.liu@nxp.com> <20260515-resourceful-singing-roadrunner-ce25ec@quoll> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 18/05/2026 06:18, Chancel Liu wrote: >>> +description: >>> + The NXP I/O connector represents a physically present I/O connector >>> +on the >>> + base board. It acts as a nexus that exposes a constrained set of >>> +I/O >>> + resources, such as GPIOs, clocks, PWMs and interrupts, through >>> +fixed >>> + electrical wiring. All actual hardware providers reside on the base board. >>> + The connector node only defines index-based mappings to those >> providers. >>> + >>> +properties: >>> + compatible: >>> + const: fsl,io-connector >> >> Everything is IO. Everything is connector, so your compatible does not match >> requirements from writing bindings. >> > > Yes, this compatible is too generic. I will rename the compatible to > fsl,aud-io-connector. aud is not much better. Which boards have it? What's the pinout? What's standard? Is it described anywhere? If so, provide reference to spec/docs. > >>> + >>> + gpio-controller: true >>> + >>> + '#gpio-cells': >>> + const: 2 >>> + >>> + gpio-map: >>> + $ref: /schemas/types.yaml#/definitions/uint32-matrix >> >> You do not need to redefine the types. You need constraints, though. >> > > OK. I will add proper constraints. > >>> + >>> + gpio-map-mask: >>> + $ref: /schemas/types.yaml#/definitions/uint32-array >>> + >>> + gpio-map-pass-thru: >>> + $ref: /schemas/types.yaml#/definitions/uint32-array >>> + >>> + '#clock-cells': >>> + const: 1 >>> + >>> + clock-map: >>> + $ref: /schemas/types.yaml#/definitions/uint32-matrix >>> + >>> + clock-map-mask: >>> + $ref: /schemas/types.yaml#/definitions/uint32-array >>> + >>> + clock-map-pass-thru: >>> + $ref: /schemas/types.yaml#/definitions/uint32-array >> >> I do not see these defined anywhere. I also checked cover letter for >> references for pulls to dtschema. >> > > Nexus nodes are already in the device-tree specification： > https://github.com/devicetree-org/devicetree-specification/blob/v0.4/source/chapter2-devicetree-basics.rst#nexus-nodes-and-specifier-mapping > For reference, current kernel has supported it: > * Nexus OF support: > commit bd6f2fd5a1d5 ("of: Support parsing phandle argument lists through a nexus node") > * GPIO adoption: > commit c11e6f0f04db ("gpio: Support gpio nexus dt bindings") > * PWM adoption: > commit e71e46a6f19c ("pwm: Add support for pwm nexus dt bindings") > Clock adoption is ongoing: > https://lore.kernel.org/all/20260327-schneider-v7-0-rc1-crypto-v1-10-5e6ff7853994@bootlin.com/ DT spec only mentions nexuses, but it is only a spec. Each property from the spec must be defined in dtschema or kernel bindings. I do not see any dependency mentioned in the cover letter, so how do you think we can figure out where is this definition of clock nexus? Best regards, Krzysztof