From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vidya Sagar Subject: Re: [PATCH V5 12/16] arm64: tegra: Add P2U and PCIe controller nodes to Tegra194 DT Date: Tue, 7 May 2019 15:40:19 +0530 Message-ID: References: <20190424052004.6270-1-vidyas@nvidia.com> <20190424052004.6270-13-vidyas@nvidia.com> <20190503112637.GF32400@ulmo> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20190503112637.GF32400@ulmo> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Thierry Reding Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com, jonathanh@nvidia.com, kishon@ti.com, catalin.marinas@arm.com, will.deacon@arm.com, jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, mperttunen@nvidia.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com List-Id: devicetree@vger.kernel.org On 5/3/2019 4:56 PM, Thierry Reding wrote: > On Wed, Apr 24, 2019 at 10:50:00AM +0530, Vidya Sagar wrote: >> Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree. >> The Tegra194 SoC contains six PCIe controllers and twenty P2U instances >> grouped into two different PHY bricks namely High-Speed IO (HSIO-12 P2Us) >> and NVIDIA High Speed (NVHS-8 P2Us) respectively. >> >> Signed-off-by: Vidya Sagar >> --- >> Changes since [v4]: >> * None >> >> Changes since [v3]: >> * None >> >> Changes since [v2]: >> * Included 'hsio' or 'nvhs' in P2U node's label names to reflect which brick >> they belong to >> * Removed leading zeros in unit address >> >> Changes since [v1]: >> * Flattened all P2U nodes by removing 'hsio-p2u' and 'nvhs-p2u' super nodes >> * Changed P2U nodes compatible string from 'nvidia,tegra194-phy-p2u' to 'nvidia,tegra194-p2u' >> * Changed reg-name from 'base' to 'ctl' >> * Updated all PCIe nodes according to the changes made to DT documentation file >> >> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 449 +++++++++++++++++++++++ >> 1 file changed, 449 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi >> index c77ca211fa8f..dc433b446ff5 100644 >> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi >> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi > [...] >> + pcie@14180000 { > [...] >> + ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ >> + 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x3 0x40000000 /* prefetchable memory (13GB) */ >> + 0x82000000 0x0 0x40000000 0x1B 0x40000000 0x0 0xC0000000>; /* non-prefetchable memory (3GB) */ > > Please be consistent in the capitalization of hexadecimal numbers. You > use lowercase hexdigits in one place and upprecase in others. Just stick > to one (preferably lowercase since that's already used elsewhere in this > file). Ok. > >> + }; >> + >> + pcie@14100000 { > > Also, entries should be sorted by unit-address, so controller 0 above > needs to go further down. Ok. > > Thierry >