[PATCH 0/5] arm64: dts: NXP: add basic dts file for LX2160A SoC

[PATCH 0/5] arm64: dts: NXP: add basic dts file for LX2160A SoC

[Vabhav Sharma]

- Add compatible string for LX2160A clockgen support
- Add compatible string to initialize LX2160A guts driver
- Add compatible string for LX2160A support in dt-bindings
- Add dts file to enable support for LX2160A SoC and LX2160A RDB
  (Reference design board)

Vabhav Sharma (4):
  dt-bindings: arm64: add compatible for LX2160A
  soc/fsl/guts: Add compatible string for LX2160A
  arm64: dts: add QorIQ LX2160A SoC support
  arm64: dts: add LX2160ARDB board support

Yogesh Gaur (1):
  drivers: clk-qoriq: Add clockgen support for lx2160a

 Documentation/devicetree/bindings/arm/fsl.txt     |  12 +
 arch/arm64/boot/dts/freescale/Makefile            |   1 +
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts |  95 ++++
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi    | 572 ++++++++++++++++++++++
 drivers/clk/clk-qoriq.c                           |  14 +-
 drivers/cpufreq/qoriq-cpufreq.c                   |   1 +
 drivers/soc/fsl/guts.c                            |   1 +
 7 files changed, 695 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi

-- 
2.7.4

[PATCH 1/5] dt-bindings: arm64: add compatible for LX2160A

[Vabhav Sharma]

Add compatible for LX2160A SoC,QDS and RDB board

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
 Documentation/devicetree/bindings/arm/fsl.txt | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index cdb9dd7..76256bd 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -218,3 +218,15 @@ Required root node properties:
 LS2088A ARMv8 based RDB Board
 Required root node properties:
     - compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
+
+LX2160A SoC
+Required root node properties:
+    - compatible = "fsl,lx2160a";
+
+LX2160A ARMv8 based QDS Board
+Required root node properties:
+    - compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
+
+LX2160A ARMv8 based RDB Board
+Required root node properties:
+    - compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
-- 
2.7.4

[PATCH 2/5] soc/fsl/guts: Add compatible string for LX2160A

[Vabhav Sharma]

Adding compatible string "lx2160a-dcfg" to
initialize guts driver for lx2160

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
 drivers/soc/fsl/guts.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
index 302e0c8..5e1e633 100644
--- a/drivers/soc/fsl/guts.c
+++ b/drivers/soc/fsl/guts.c
@@ -222,6 +222,7 @@ static const struct of_device_id fsl_guts_of_match[] = {
 	{ .compatible = "fsl,ls1088a-dcfg", },
 	{ .compatible = "fsl,ls1012a-dcfg", },
 	{ .compatible = "fsl,ls1046a-dcfg", },
+	{ .compatible = "fsl,lx2160a-dcfg", },
 	{}
 };
 MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
-- 
2.7.4

[PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

[Vabhav Sharma]

From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>

Add clockgen support for lx2160a.
Added entry for compat 'fsl,lx2160a-clockgen'.
As LX2160A is 16 core, so modified value for NUM_CMUX

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
 drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
 drivers/cpufreq/qoriq-cpufreq.c |  1 +
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 3a1812f..fc6e308 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -60,7 +60,7 @@ struct clockgen_muxinfo {
 };
 
 #define NUM_HWACCEL	5
-#define NUM_CMUX	8
+#define NUM_CMUX	16
 
 struct clockgen;
 
@@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
 		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
 	},
 	{
+		.compat = "fsl,lx2160a-clockgen",
+		.cmux_groups = {
+			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
+		},
+		.cmux_to_group = {
+			0, 0, 0, 0, 1, 1, 1, 1, -1
+		},
+		.pll_mask = 0x37,
+		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
+	},
+	{
 		.compat = "fsl,p2041-clockgen",
 		.guts_compat = "fsl,qoriq-device-config-1.0",
 		.init_periph = p2041_init_periph,
@@ -1424,6 +1435,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
 CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
+CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
 
 /* Legacy nodes */
 CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
diff --git a/drivers/cpufreq/qoriq-cpufreq.c b/drivers/cpufreq/qoriq-cpufreq.c
index 3d773f6..83921b7 100644
--- a/drivers/cpufreq/qoriq-cpufreq.c
+++ b/drivers/cpufreq/qoriq-cpufreq.c
@@ -295,6 +295,7 @@ static const struct of_device_id node_matches[] __initconst = {
 	{ .compatible = "fsl,ls1046a-clockgen", },
 	{ .compatible = "fsl,ls1088a-clockgen", },
 	{ .compatible = "fsl,ls2080a-clockgen", },
+	{ .compatible = "fsl,lx2160a-clockgen", },
 	{ .compatible = "fsl,p4080-clockgen", },
 	{ .compatible = "fsl,qoriq-clockgen-1.0", },
 	{ .compatible = "fsl,qoriq-clockgen-2.0", },
-- 
2.7.4

Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

[Stephen Boyd]

Quoting Vabhav Sharma (2018-08-19 23:47:14)
> From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> 
> Add clockgen support for lx2160a.
> Added entry for compat 'fsl,lx2160a-clockgen'.
> As LX2160A is 16 core, so modified value for NUM_CMUX
> 
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> ---

Acked-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

[Scott Wood]

On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> 
> Add clockgen support for lx2160a.
> Added entry for compat 'fsl,lx2160a-clockgen'.
> As LX2160A is 16 core, so modified value for NUM_CMUX
> 
> Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> ---
>  drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
>  drivers/cpufreq/qoriq-cpufreq.c |  1 +
>  2 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
> index 3a1812f..fc6e308 100644
> --- a/drivers/clk/clk-qoriq.c
> +++ b/drivers/clk/clk-qoriq.c
> @@ -60,7 +60,7 @@ struct clockgen_muxinfo {
>  };
>  
>  #define NUM_HWACCEL	5
> -#define NUM_CMUX	8
> +#define NUM_CMUX	16
>  
>  struct clockgen;
>  
> @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
>  		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
>  	},
>  	{
> +		.compat = "fsl,lx2160a-clockgen",
> +		.cmux_groups = {
> +			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> +		},
> +		.cmux_to_group = {
> +			0, 0, 0, 0, 1, 1, 1, 1, -1
> +		},
> +		.pll_mask = 0x37,
> +		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> +	},

Why are you increasing NUM_CMUX beyond 8 for a chip that only has 8 entries in
cmux_to_group?

-Scott

RE: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

[Vabhav Sharma]

> -----Original Message-----
> From: linux-kernel-owner@vger.kernel.org <linux-kernel-
> owner@vger.kernel.org> On Behalf Of Scott Wood
> Sent: Wednesday, August 29, 2018 5:49 AM
> To: Vabhav Sharma <vabhav.sharma@nxp.com>; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; robh+dt@kernel.org;
> mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org; linux-arm-
> kernel@lists.infradead.org; mturquette@baylibre.com; sboyd@kernel.org;
> rjw@rjwysocki.net; viresh.kumar@linaro.org; linux-clk@vger.kernel.org;
> linux-pm@vger.kernel.org; linux-kernel-owner@vger.kernel.org;
> catalin.marinas@arm.com; will.deacon@arm.com;
> gregkh@linuxfoundation.org; arnd@arndb.de;
> kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Andy Tang
> <andy.tang@nxp.com>; Udit Kumar <udit.kumar@nxp.com>;
> linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>
> Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a
> 
> On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> >
> > Add clockgen support for lx2160a.
> > Added entry for compat 'fsl,lx2160a-clockgen'.
> > As LX2160A is 16 core, so modified value for NUM_CMUX
> >
> > Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > ---
> >  drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
> >  drivers/cpufreq/qoriq-cpufreq.c |  1 +
> >  2 files changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > 3a1812f..fc6e308 100644
> > --- a/drivers/clk/clk-qoriq.c
> > +++ b/drivers/clk/clk-qoriq.c
> > @@ -60,7 +60,7 @@ struct clockgen_muxinfo {  };
> >
> >  #define NUM_HWACCEL	5
> > -#define NUM_CMUX	8
> > +#define NUM_CMUX	16
> >
> >  struct clockgen;
> >
> > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
> >  		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> >  	},
> >  	{
> > +		.compat = "fsl,lx2160a-clockgen",
> > +		.cmux_groups = {
> > +			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > +		},
> > +		.cmux_to_group = {
> > +			0, 0, 0, 0, 1, 1, 1, 1, -1
> > +		},
> > +		.pll_mask = 0x37,
> > +		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > +	},
> 
> Why are you increasing NUM_CMUX beyond 8 for a chip that only has 8
> entries in cmux_to_group?
Configuration is 16 cores,8 cluster with 2 cores in each cluster
> 
> -Scott

Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

[Scott Wood]

On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > -----Original Message-----
> > From: linux-kernel-owner@vger.kernel.org <linux-kernel-
> > owner@vger.kernel.org> On Behalf Of Scott Wood
> > Sent: Wednesday, August 29, 2018 5:49 AM
> > To: Vabhav Sharma <vabhav.sharma@nxp.com>; linux-
> > kernel@vger.kernel.org; devicetree@vger.kernel.org; robh+dt@kernel.org;
> > mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org; linux-arm-
> > kernel@lists.infradead.org; mturquette@baylibre.com; sboyd@kernel.org;
> > rjw@rjwysocki.net; viresh.kumar@linaro.org; linux-clk@vger.kernel.org;
> > linux-pm@vger.kernel.org; linux-kernel-owner@vger.kernel.org;
> > catalin.marinas@arm.com; will.deacon@arm.com;
> > gregkh@linuxfoundation.org; arnd@arndb.de;
> > kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> > Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Andy Tang
> > <andy.tang@nxp.com>; Udit Kumar <udit.kumar@nxp.com>;
> > linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>
> > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> > lx2160a
> > 
> > On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > > From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > 
> > > Add clockgen support for lx2160a.
> > > Added entry for compat 'fsl,lx2160a-clockgen'.
> > > As LX2160A is 16 core, so modified value for NUM_CMUX
> > > 
> > > Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > > ---
> > >  drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
> > >  drivers/cpufreq/qoriq-cpufreq.c |  1 +
> > >  2 files changed, 14 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > > 3a1812f..fc6e308 100644
> > > --- a/drivers/clk/clk-qoriq.c
> > > +++ b/drivers/clk/clk-qoriq.c
> > > @@ -60,7 +60,7 @@ struct clockgen_muxinfo {  };
> > > 
> > >  #define NUM_HWACCEL	5
> > > -#define NUM_CMUX	8
> > > +#define NUM_CMUX	16
> > > 
> > >  struct clockgen;
> > > 
> > > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[] =
> > > {
> > >  		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > >  	},
> > >  	{
> > > +		.compat = "fsl,lx2160a-clockgen",
> > > +		.cmux_groups = {
> > > +			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > > +		},
> > > +		.cmux_to_group = {
> > > +			0, 0, 0, 0, 1, 1, 1, 1, -1
> > > +		},
> > > +		.pll_mask = 0x37,
> > > +		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > +	},
> > 
> > Why are you increasing NUM_CMUX beyond 8 for a chip that only has 8
> > entries in cmux_to_group?
> 
> Configuration is 16 cores,8 cluster with 2 cores in each cluster

So?  This is about cmuxes, not cores.  You're increasing the array without
ever using the new size.

-Scott

Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

[Scott Wood]

On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote:
> On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > > -----Original Message-----
> > > From: linux-kernel-owner@vger.kernel.org <linux-kernel-
> > > owner@vger.kernel.org> On Behalf Of Scott Wood
> > > Sent: Wednesday, August 29, 2018 5:49 AM
> > > To: Vabhav Sharma <vabhav.sharma@nxp.com>; linux-
> > > kernel@vger.kernel.org; devicetree@vger.kernel.org; robh+dt@kernel.org;
> > > mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org; linux-arm-
> > > kernel@lists.infradead.org; mturquette@baylibre.com; sboyd@kernel.org;
> > > rjw@rjwysocki.net; viresh.kumar@linaro.org; linux-clk@vger.kernel.org;
> > > linux-pm@vger.kernel.org; linux-kernel-owner@vger.kernel.org;
> > > catalin.marinas@arm.com; will.deacon@arm.com;
> > > gregkh@linuxfoundation.org; arnd@arndb.de;
> > > kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> > > Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Andy Tang
> > > <andy.tang@nxp.com>; Udit Kumar <udit.kumar@nxp.com>;
> > > linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>
> > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> > > lx2160a
> > > 
> > > On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > > > From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > > 
> > > > Add clockgen support for lx2160a.
> > > > Added entry for compat 'fsl,lx2160a-clockgen'.
> > > > As LX2160A is 16 core, so modified value for NUM_CMUX
> > > > 
> > > > Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> > > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > > > ---
> > > >  drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
> > > >  drivers/cpufreq/qoriq-cpufreq.c |  1 +
> > > >  2 files changed, 14 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c index
> > > > 3a1812f..fc6e308 100644
> > > > --- a/drivers/clk/clk-qoriq.c
> > > > +++ b/drivers/clk/clk-qoriq.c
> > > > @@ -60,7 +60,7 @@ struct clockgen_muxinfo {  };
> > > > 
> > > >  #define NUM_HWACCEL	5
> > > > -#define NUM_CMUX	8
> > > > +#define NUM_CMUX	16
> > > > 
> > > >  struct clockgen;
> > > > 
> > > > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo chipinfo[]
> > > > =
> > > > {
> > > >  		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > >  	},
> > > >  	{
> > > > +		.compat = "fsl,lx2160a-clockgen",
> > > > +		.cmux_groups = {
> > > > +			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > > > +		},
> > > > +		.cmux_to_group = {
> > > > +			0, 0, 0, 0, 1, 1, 1, 1, -1
> > > > +		},
> > > > +		.pll_mask = 0x37,
> > > > +		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > > +	},
> > > 
> > > Why are you increasing NUM_CMUX beyond 8 for a chip that only has 8
> > > entries in cmux_to_group?
> > 
> > Configuration is 16 cores,8 cluster with 2 cores in each cluster
> 
> So?  This is about cmuxes, not cores.  You're increasing the array without
> ever using the new size.

Oh, and you also broke p4080 which has 8 cmuxes but no -1 terminator, because
the array was of length 8.  Probably the array should be changed to NUM_CMUX+1
so every array can be -1 terminated.

-Scott

RE: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

[Andy Tang]

Hi Scott,

Please see my replay inline.

> -----Original Message-----
> From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org>
> On Behalf Of Scott Wood
> Sent: 2018年8月31日 1:43
> To: Vabhav Sharma <vabhav.sharma@nxp.com>;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> robh+dt@kernel.org; mark.rutland@arm.com;
> linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> mturquette@baylibre.com; sboyd@kernel.org; rjw@rjwysocki.net;
> viresh.kumar@linaro.org; linux-clk@vger.kernel.org;
> linux-pm@vger.kernel.org; linux-kernel-owner@vger.kernel.org;
> catalin.marinas@arm.com; will.deacon@arm.com;
> gregkh@linuxfoundation.org; arnd@arndb.de;
> kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Andy Tang
> <andy.tang@nxp.com>; linux@armlinux.org.uk; Varun Sethi
> <V.Sethi@nxp.com>; Udit Kumar <udit.kumar@nxp.com>
> Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> lx2160a
> 
> On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote:
> > On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > > > -----Original Message-----
> > > > From: linux-kernel-owner@vger.kernel.org <linux-kernel-
> > > > owner@vger.kernel.org> On Behalf Of Scott Wood
> > > > Sent: Wednesday, August 29, 2018 5:49 AM
> > > > To: Vabhav Sharma <vabhav.sharma@nxp.com>; linux-
> > > > kernel@vger.kernel.org; devicetree@vger.kernel.org;
> > > > robh+dt@kernel.org; mark.rutland@arm.com;
> > > > linuxppc-dev@lists.ozlabs.org; linux-arm-
> > > > kernel@lists.infradead.org; mturquette@baylibre.com;
> > > > sboyd@kernel.org; rjw@rjwysocki.net; viresh.kumar@linaro.org;
> > > > linux-clk@vger.kernel.org; linux-pm@vger.kernel.org;
> > > > linux-kernel-owner@vger.kernel.org;
> > > > catalin.marinas@arm.com; will.deacon@arm.com;
> > > > gregkh@linuxfoundation.org; arnd@arndb.de;
> > > > kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> > > > Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Andy
> Tang
> > > > <andy.tang@nxp.com>; Udit Kumar <udit.kumar@nxp.com>;
> > > > linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>
> > > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support
> > > > for lx2160a
> > > >
> > > > On Mon, 2018-08-20 at 12:17 +0530, Vabhav Sharma wrote:
> > > > > From: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > > >
> > > > > Add clockgen support for lx2160a.
> > > > > Added entry for compat 'fsl,lx2160a-clockgen'.
> > > > > As LX2160A is 16 core, so modified value for NUM_CMUX
> > > > >
> > > > > Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
> > > > > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > > > > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > > > > ---
> > > > >  drivers/clk/clk-qoriq.c         | 14 +++++++++++++-
> > > > >  drivers/cpufreq/qoriq-cpufreq.c |  1 +
> > > > >  2 files changed, 14 insertions(+), 1 deletion(-)
> > > > >
> > > > > diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
> > > > > index
> > > > > 3a1812f..fc6e308 100644
> > > > > --- a/drivers/clk/clk-qoriq.c
> > > > > +++ b/drivers/clk/clk-qoriq.c
> > > > > @@ -60,7 +60,7 @@ struct clockgen_muxinfo {  };
> > > > >
> > > > >  #define NUM_HWACCEL	5
> > > > > -#define NUM_CMUX	8
> > > > > +#define NUM_CMUX	16
> > > > >
> > > > >  struct clockgen;
> > > > >
> > > > > @@ -570,6 +570,17 @@ static const struct clockgen_chipinfo
> > > > > chipinfo[] = {
> > > > >  		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > > >  	},
> > > > >  	{
> > > > > +		.compat = "fsl,lx2160a-clockgen",
> > > > > +		.cmux_groups = {
> > > > > +			&clockgen2_cmux_cga12, &clockgen2_cmux_cgb
> > > > > +		},
> > > > > +		.cmux_to_group = {
> > > > > +			0, 0, 0, 0, 1, 1, 1, 1, -1
> > > > > +		},
> > > > > +		.pll_mask = 0x37,
> > > > > +		.flags = CG_VER3 | CG_LITTLE_ENDIAN,
> > > > > +	},
> > > >
> > > > Why are you increasing NUM_CMUX beyond 8 for a chip that only
> has
> > > > 8 entries in cmux_to_group?
> > >
> > > Configuration is 16 cores,8 cluster with 2 cores in each cluster
> >
> > So?  This is about cmuxes, not cores.  You're increasing the array
> > without ever using the new size.
> 
> Oh, and you also broke p4080 which has 8 cmuxes but no -1 terminator,
> because the array was of length 8.  Probably the array should be changed
> to NUM_CMUX+1 so every array can be -1 terminated.
> 
[Andy] How about we add -1 terminator to p4080 and increase NUM_CMUX to 16?
We don't want to increase NUM_CMUX each time new soc with more cmuxes added.

BR,
Andy Tang

> -Scott
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flist
> s.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&amp;data=02
> %7C01%7Candy.tang%40nxp.com%7C963d0cdf49964539ea4408d60ea06
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> 3IoLTOw%3D&amp;reserved=0

Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

[Scott Wood]

On Fri, 2018-08-31 at 06:12 +0000, Andy Tang wrote:
> Hi Scott,
> 
> Please see my replay inline.
> 
> > -----Original Message-----
> > From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org>
> > On Behalf Of Scott Wood
> > Sent: 2018年8月31日 1:43
> > To: Vabhav Sharma <vabhav.sharma@nxp.com>;
> > linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> > robh+dt@kernel.org; mark.rutland@arm.com;
> > linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> > mturquette@baylibre.com; sboyd@kernel.org; rjw@rjwysocki.net;
> > viresh.kumar@linaro.org; linux-clk@vger.kernel.org;
> > linux-pm@vger.kernel.org; linux-kernel-owner@vger.kernel.org;
> > catalin.marinas@arm.com; will.deacon@arm.com;
> > gregkh@linuxfoundation.org; arnd@arndb.de;
> > kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> > Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Andy Tang
> > <andy.tang@nxp.com>; linux@armlinux.org.uk; Varun Sethi
> > <V.Sethi@nxp.com>; Udit Kumar <udit.kumar@nxp.com>
> > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> > lx2160a
> > 
> > On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote:
> > > On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > > > > 
> > > > > Why are you increasing NUM_CMUX beyond 8 for a chip that only
> > 
> > has
> > > > > 8 entries in cmux_to_group?
> > > > 
> > > > Configuration is 16 cores,8 cluster with 2 cores in each cluster
> > > 
> > > So?  This is about cmuxes, not cores.  You're increasing the array
> > > without ever using the new size.
> > 
> > Oh, and you also broke p4080 which has 8 cmuxes but no -1 terminator,
> > because the array was of length 8.  Probably the array should be changed
> > to NUM_CMUX+1 so every array can be -1 terminated.
> > 
> 
> [Andy] How about we add -1 terminator to p4080 and increase NUM_CMUX to 16?

Why 16?  What does such a change have to do with this chip, which according to
the rest of the patch has 8 cmuxes?

> We don't want to increase NUM_CMUX each time new soc with more cmuxes added.

You don't want to have to make a trivial change each time you exceed a limit
that has yet to be exceeded once since NUM_CMUX was added?  This isn't ABI or
in any other way hard to change.  It's right in the same file as the chip
description you'd be adding.

And even if a chip did come along with 16 cmuxes, you'd then need to increase
the array to 17 to hold the -1 if you don't want to leave a situation like the
p4080 is in now, where a chip's cmux array could be broken by increasing
NUM_CMUX further.

-Scott

RE: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

[Andy Tang]

Hi Scott,

Please see my replay in line.

> -----Original Message-----
> From: Linuxppc-dev
> <linuxppc-dev-bounces+b29983=freescale.com@lists.ozlabs.org> On
> Behalf Of Scott Wood
> Sent: 2018年9月1日 4:29
> To: Andy Tang <andy.tang@nxp.com>; Vabhav Sharma
> <vabhav.sharma@nxp.com>; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; robh+dt@kernel.org;
> mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org;
> linux-arm-kernel@lists.infradead.org; mturquette@baylibre.com;
> sboyd@kernel.org; rjw@rjwysocki.net; viresh.kumar@linaro.org;
> linux-clk@vger.kernel.org; linux-pm@vger.kernel.org;
> linux-kernel-owner@vger.kernel.org; catalin.marinas@arm.com;
> will.deacon@arm.com; gregkh@linuxfoundation.org; arnd@arndb.de;
> kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>;
> linux@armlinux.org.uk; Udit Kumar <udit.kumar@nxp.com>; Varun Sethi
> <V.Sethi@nxp.com>
> Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> lx2160a
> 
> On Fri, 2018-08-31 at 06:12 +0000, Andy Tang wrote:
> > Hi Scott,
> >
> > Please see my replay inline.
> >
> > > -----Original Message-----
> > > From: linux-arm-kernel
> > > <linux-arm-kernel-bounces@lists.infradead.org>
> > > On Behalf Of Scott Wood
> > > Sent: 2018年8月31日 1:43
> > > To: Vabhav Sharma <vabhav.sharma@nxp.com>;
> > > linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> > > robh+dt@kernel.org; mark.rutland@arm.com;
> > > linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> > > mturquette@baylibre.com; sboyd@kernel.org; rjw@rjwysocki.net;
> > > viresh.kumar@linaro.org; linux-clk@vger.kernel.org;
> > > linux-pm@vger.kernel.org; linux-kernel-owner@vger.kernel.org;
> > > catalin.marinas@arm.com; will.deacon@arm.com;
> > > gregkh@linuxfoundation.org; arnd@arndb.de;
> > > kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> > > Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Andy Tang
> > > <andy.tang@nxp.com>; linux@armlinux.org.uk; Varun Sethi
> > > <V.Sethi@nxp.com>; Udit Kumar <udit.kumar@nxp.com>
> > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support
> > > for lx2160a
> > >
> > > On Thu, 2018-08-30 at 12:39 -0500, Scott Wood wrote:
> > > > On Thu, 2018-08-30 at 07:36 +0000, Vabhav Sharma wrote:
> > > > > >
> > > > > > Why are you increasing NUM_CMUX beyond 8 for a chip that
> only
> > >
> > > has
> > > > > > 8 entries in cmux_to_group?
> > > > >
> > > > > Configuration is 16 cores,8 cluster with 2 cores in each cluster
> > > >
> > > > So?  This is about cmuxes, not cores.  You're increasing the array
> > > > without ever using the new size.
> > >
> > > Oh, and you also broke p4080 which has 8 cmuxes but no -1
> > > terminator, because the array was of length 8.  Probably the array
> > > should be changed to NUM_CMUX+1 so every array can be -1
> terminated.
> > >
> >
> > [Andy] How about we add -1 terminator to p4080 and increase
> NUM_CMUX to 16?
> 
> Why 16?  What does such a change have to do with this chip, which
> according to the rest of the patch has 8 cmuxes?
[Andy] NUM_CMUX is a limitation number. We better give it an extra buffer, not exactly equal to the limitation.
16 is the limitation number with extra buffer.

> 
> > We don't want to increase NUM_CMUX each time new soc with more
> cmuxes added.
> 
> You don't want to have to make a trivial change each time you exceed a
> limit that has yet to be exceeded once since NUM_CMUX was added?
> This isn't ABI or in any other way hard to change.  It's right in the same file
> as the chip description you'd be adding.
> 
> And even if a chip did come along with 16 cmuxes, you'd then need to
> increase the array to 17 to hold the -1 if you don't want to leave a situation
> like the
> p4080 is in now, where a chip's cmux array could be broken by increasing
> NUM_CMUX further.
> 
[Andy] Adding buffer to a limitation number is always a good habit when coding. We often forget to increase this value when
a new chip with more cmuxes added. Like this patch, we didn't increase this value at first. We spent a lot of time finding out that NUM_CMUX needs to be increased too.
It is a personal preference how to set this value. I think it is better to increase it to 16, not NUM_CMUX+1 as long as we fix the P4080 issue
even though it is a trivial change. And I agree the description needs to be updated.

BR,
Andy

> -Scott

Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

[Scott Wood]

On Mon, 2018-09-03 at 01:17 +0000, Andy Tang wrote:
> Hi Scott,
> 
> Please see my replay in line.
> 
> > -----Original Message-----
> > From: Linuxppc-dev
> > <linuxppc-dev-bounces+b29983=freescale.com@lists.ozlabs.org> On
> > Behalf Of Scott Wood
> > Sent: 2018年9月1日 4:29
> > To: Andy Tang <andy.tang@nxp.com>; Vabhav Sharma
> > <vabhav.sharma@nxp.com>; linux-kernel@vger.kernel.org;
> > devicetree@vger.kernel.org; robh+dt@kernel.org;
> > mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org;
> > linux-arm-kernel@lists.infradead.org; mturquette@baylibre.com;
> > sboyd@kernel.org; rjw@rjwysocki.net; viresh.kumar@linaro.org;
> > linux-clk@vger.kernel.org; linux-pm@vger.kernel.org;
> > linux-kernel-owner@vger.kernel.org; catalin.marinas@arm.com;
> > will.deacon@arm.com; gregkh@linuxfoundation.org; arnd@arndb.de;
> > kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> > Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>;
> > linux@armlinux.org.uk; Udit Kumar <udit.kumar@nxp.com>; Varun Sethi
> > <V.Sethi@nxp.com>
> > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> > lx2160a
> > 
> > On Fri, 2018-08-31 at 06:12 +0000, Andy Tang wrote:
> > > We don't want to increase NUM_CMUX each time new soc with more
> > 
> > cmuxes added.
> > 
> > You don't want to have to make a trivial change each time you exceed a
> > limit that has yet to be exceeded once since NUM_CMUX was added?
> > This isn't ABI or in any other way hard to change.  It's right in the same
> > file
> > as the chip description you'd be adding.
> > 
> > And even if a chip did come along with 16 cmuxes, you'd then need to
> > increase the array to 17 to hold the -1 if you don't want to leave a
> > situation
> > like the
> > p4080 is in now, where a chip's cmux array could be broken by increasing
> > NUM_CMUX further.
> > 
> 
> [Andy] Adding buffer to a limitation number is always a good habit when
> coding. We often forget to increase this value when
> a new chip with more cmuxes added. 

"often"?  There has never been a new chip added with more cmuxes than p4080's
8, and if one does come along and you forget, the compiler should complain
about exceeding the array length with a static initializer.  This isn't like
an array that is filled with a runtime-determined length.

> Like this patch, we didn't increase this value at first. We spent a lot of
> time finding out that NUM_CMUX needs to be increased too.

Are you talking about some other chip that you haven't sent a patch for yet? 
Or is the cmux array for this chip wrong?  What specifically did you see
happen "at first"?

> It is a personal preference how to set this value. I think it is better to
> increase it to 16, not NUM_CMUX+1 as long as we fix the P4080 issue
> even though it is a trivial change. And I agree the description needs to be
> updated.

I'm not the clock maintainer, so it's not up to me, but I don't see the point
in setting it to an arbitrary number, and I do not agree that increasing
NUM_CMUX is a suitable replacement for NUM_CMUX+1 in cmux_to_group[], as that
array should be one larger than cmux[] in order to allow every chip to have a
-1 terminator.  In any case, any change to NUM_CMUX should be a separate patch
because it's not required for lx2160a support (assuming lx2160a was correctly
described by this patch).

-Scott



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

RE: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for lx2160a

[Andy Tang]

Hi Scott,

Please see my replay inline.

> -----Original Message-----
> From: linux-arm-kernel <linux-arm-kernel-bounces@lists.infradead.org>
> On Behalf Of Scott Wood
> Sent: 2018年9月4日 4:34
> To: Andy Tang <andy.tang@nxp.com>; Vabhav Sharma
> <vabhav.sharma@nxp.com>; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; robh+dt@kernel.org;
> mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org;
> linux-arm-kernel@lists.infradead.org; mturquette@baylibre.com;
> sboyd@kernel.org; rjw@rjwysocki.net; viresh.kumar@linaro.org;
> linux-clk@vger.kernel.org; linux-pm@vger.kernel.org;
> linux-kernel-owner@vger.kernel.org; catalin.marinas@arm.com;
> will.deacon@arm.com; gregkh@linuxfoundation.org; arnd@arndb.de;
> kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>;
> linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>; Udit Kumar
> <udit.kumar@nxp.com>
> Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support for
> lx2160a
> 
> On Mon, 2018-09-03 at 01:17 +0000, Andy Tang wrote:
> > Hi Scott,
> >
> > Please see my replay in line.
> >
> > > -----Original Message-----
> > > From: Linuxppc-dev
> > > <linuxppc-dev-bounces+b29983=freescale.com@lists.ozlabs.org> On
> > > Behalf Of Scott Wood
> > > Sent: 2018年9月1日 4:29
> > > To: Andy Tang <andy.tang@nxp.com>; Vabhav Sharma
> > > <vabhav.sharma@nxp.com>; linux-kernel@vger.kernel.org;
> > > devicetree@vger.kernel.org; robh+dt@kernel.org;
> > > mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org;
> > > linux-arm-kernel@lists.infradead.org; mturquette@baylibre.com;
> > > sboyd@kernel.org; rjw@rjwysocki.net; viresh.kumar@linaro.org;
> > > linux-clk@vger.kernel.org; linux-pm@vger.kernel.org;
> > > linux-kernel-owner@vger.kernel.org; catalin.marinas@arm.com;
> > > will.deacon@arm.com; gregkh@linuxfoundation.org; arnd@arndb.de;
> > > kstewart@linuxfoundation.org; yamada.masahiro@socionext.com
> > > Cc: Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com>;
> > > linux@armlinux.org.uk; Udit Kumar <udit.kumar@nxp.com>; Varun
> Sethi
> > > <V.Sethi@nxp.com>
> > > Subject: Re: [PATCH 3/5] drivers: clk-qoriq: Add clockgen support
> > > for lx2160a
> > >
> > > On Fri, 2018-08-31 at 06:12 +0000, Andy Tang wrote:
> > > > We don't want to increase NUM_CMUX each time new soc with
> more
> > >
> > > cmuxes added.
> > >
> > > You don't want to have to make a trivial change each time you exceed
> > > a limit that has yet to be exceeded once since NUM_CMUX was added?
> > > This isn't ABI or in any other way hard to change.  It's right in
> > > the same file as the chip description you'd be adding.
> > >
> > > And even if a chip did come along with 16 cmuxes, you'd then need to
> > > increase the array to 17 to hold the -1 if you don't want to leave a
> > > situation like the
> > > p4080 is in now, where a chip's cmux array could be broken by
> > > increasing NUM_CMUX further.
> > >
> >
> > [Andy] Adding buffer to a limitation number is always a good habit
> > when coding. We often forget to increase this value when a new chip
> > with more cmuxes added.
> 
> "often"?  There has never been a new chip added with more cmuxes
> than p4080's 8, and if one does come along and you forget, the compiler
> should complain about exceeding the array length with a static initializer.
> This isn't like an array that is filled with a runtime-determined length.
> 
> > Like this patch, we didn't increase this value at first. We spent a
> > lot of time finding out that NUM_CMUX needs to be increased too.
> 
> Are you talking about some other chip that you haven't sent a patch for
> yet?
> Or is the cmux array for this chip wrong?  What specifically did you see
> happen "at first"?
> 
[Andy] Sorry, "Often" is not a right word. I meant we tend to add new soc without updating NUM_CMUX.
 
> > It is a personal preference how to set this value. I think it is
> > better to increase it to 16, not NUM_CMUX+1 as long as we fix the
> > P4080 issue even though it is a trivial change. And I agree the
> > description needs to be updated.
> 
> I'm not the clock maintainer, so it's not up to me, but I don't see the point
> in setting it to an arbitrary number, and I do not agree that increasing
> NUM_CMUX is a suitable replacement for NUM_CMUX+1 in
> cmux_to_group[], as that array should be one larger than cmux[] in order
> to allow every chip to have a
> -1 terminator.  In any case, any change to NUM_CMUX should be a
> separate patch because it's not required for lx2160a support (assuming
> lx2160a was correctly described by this patch).
[Andy] I don't see any impropriate about your suggestion. so we are going to do in your way.

Thanks,
Andy
> 
> -Scott
> 
> 
> 
> _______________________________________________
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> 8060797113&amp;sdata=iCLKGMEzRX2dpH5%2Bf4NWIiPDc5L5NpTcpZ7X
> usehdIw%3D&amp;reserved=0

[PATCH 4/5] arm64: dts: add QorIQ LX2160A SoC support

[Vabhav Sharma]

LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.

LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores
in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C
controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA
UARTs etc.

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 572 +++++++++++++++++++++++++
 1 file changed, 572 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
new file mode 100644
index 0000000..e35e494
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -0,0 +1,572 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree Include file for Layerscape-LX2160A family SoC.
+//
+// Copyright 2018 NXP
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/memreserve/ 0x80000000 0x00010000;
+
+/ {
+	compatible = "fsl,lx2160a";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		// 8 clusters having 2 Cortex-A72 cores each
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x0>;
+			clocks = <&clockgen 1 0>;
+			next-level-cache = <&cluster0_l2>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x1>;
+			clocks = <&clockgen 1 0>;
+			next-level-cache = <&cluster0_l2>;
+		};
+
+		cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x100>;
+			clocks = <&clockgen 1 1>;
+			next-level-cache = <&cluster1_l2>;
+		};
+
+		cpu@101 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x101>;
+			clocks = <&clockgen 1 1>;
+			next-level-cache = <&cluster1_l2>;
+		};
+
+		cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x200>;
+			clocks = <&clockgen 1 2>;
+			next-level-cache = <&cluster2_l2>;
+		};
+
+		cpu@201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x201>;
+			clocks = <&clockgen 1 2>;
+			next-level-cache = <&cluster2_l2>;
+		};
+
+		cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x300>;
+			clocks = <&clockgen 1 3>;
+			next-level-cache = <&cluster3_l2>;
+		};
+
+		cpu@301 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x301>;
+			clocks = <&clockgen 1 3>;
+			next-level-cache = <&cluster3_l2>;
+		};
+
+		cpu@400 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x400>;
+			clocks = <&clockgen 1 4>;
+			next-level-cache = <&cluster4_l2>;
+		};
+
+		cpu@401 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x401>;
+			clocks = <&clockgen 1 4>;
+			next-level-cache = <&cluster4_l2>;
+		};
+
+		cpu@500 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x500>;
+			clocks = <&clockgen 1 5>;
+			next-level-cache = <&cluster5_l2>;
+		};
+
+		cpu@501 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x501>;
+			clocks = <&clockgen 1 5>;
+			next-level-cache = <&cluster5_l2>;
+		};
+
+		cpu@600 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x600>;
+			clocks = <&clockgen 1 6>;
+			next-level-cache = <&cluster6_l2>;
+		};
+
+		cpu@601 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x601>;
+			clocks = <&clockgen 1 6>;
+			next-level-cache = <&cluster6_l2>;
+		};
+
+		cpu@700 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x700>;
+			clocks = <&clockgen 1 7>;
+			next-level-cache = <&cluster7_l2>;
+		};
+
+		cpu@701 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0x701>;
+			clocks = <&clockgen 1 7>;
+			next-level-cache = <&cluster7_l2>;
+		};
+
+		cluster0_l2: l2-cache0 {
+			compatible = "cache";
+		};
+
+		cluster1_l2: l2-cache1 {
+			compatible = "cache";
+		};
+
+		cluster2_l2: l2-cache2 {
+			compatible = "cache";
+		};
+
+		cluster3_l2: l2-cache3 {
+			compatible = "cache";
+		};
+
+		cluster4_l2: l2-cache4 {
+			compatible = "cache";
+		};
+
+		cluster5_l2: l2-cache5 {
+			compatible = "cache";
+		};
+
+		cluster6_l2: l2-cache6 {
+			compatible = "cache";
+		};
+
+		cluster7_l2: l2-cache7 {
+			compatible = "cache";
+		};
+	};
+
+	gic: interrupt-controller@6000000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
+			<0x0 0x06200000 0 0x200000>, // GICR (RD_base +
+						     // SGI_base)
+			<0x0 0x0c0c0000 0 0x2000>, // GICC
+			<0x0 0x0c0d0000 0 0x1000>, // GICH
+			<0x0 0x0c0e0000 0 0x20000>; // GICV
+		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		interrupt-controller;
+		interrupts = <1 9 0x4>;
+
+		its: gic-its@6020000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x6020000 0 0x20000>;
+		};
+	};
+
+	rstcr: syscon@1e60000 {
+		compatible = "syscon";
+		reg = <0x0 0x1e60000 0x0 0x4>;
+	};
+
+	reboot {
+		compatible ="syscon-reboot";
+		regmap = <&rstcr>;
+		offset = <0x0>;
+		mask = <0x2>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <1 13 4>, // Physical Secure PPI, active-low
+			     <1 14 4>, // Physical Non-Secure PPI, active-low
+			     <1 11 4>, // Virtual PPI, active-low
+			     <1 10 4>; // Hypervisor PPI, active-low
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <1 7 0x8>; // PMU PPI, Level low type
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	memory@80000000 {
+		// DRAM space - 1, size : 2 GB DRAM
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0 0x80000000>;
+	};
+
+	ddr1: memory-controller@1080000 {
+		compatible = "fsl,qoriq-memory-controller";
+		reg = <0x0 0x1080000 0x0 0x1000>;
+		interrupts = <0 17 0x4>;
+		little-endian;
+	};
+
+	ddr2: memory-controller@1090000 {
+		compatible = "fsl,qoriq-memory-controller";
+		reg = <0x0 0x1090000 0x0 0x1000>;
+		interrupts = <0 18 0x4>;
+		little-endian;
+	};
+
+	sysclk: sysclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "sysclk";
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		clockgen: clocking@1300000 {
+			compatible = "fsl,lx2160a-clockgen";
+			reg = <0 0x1300000 0 0xa0000>;
+			#clock-cells = <2>;
+			clocks = <&sysclk>;
+		};
+
+		crypto: crypto@8000000 {
+			compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
+			fsl,sec-era = <10>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x00 0x8000000 0x100000>;
+			reg = <0x00 0x8000000 0x0 0x100000>;
+			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
+			status = "disabled";
+
+			sec_jr0: jr@10000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg        = <0x10000 0x10000>;
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr1: jr@20000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg        = <0x20000 0x10000>;
+				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr2: jr@30000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg        = <0x30000 0x10000>;
+				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			sec_jr3: jr@40000 {
+				compatible = "fsl,sec-v5.0-job-ring",
+					     "fsl,sec-v4.0-job-ring";
+				reg        = <0x40000 0x10000>;
+				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		dcfg: dcfg@1e00000 {
+			compatible = "fsl,lx2160a-dcfg", "syscon";
+			reg = <0x0 0x1e00000 0x0 0x10000>;
+			little-endian;
+		};
+
+		gpio0: gpio@2300000 {
+			compatible = "fsl,qoriq-gpio";
+			reg = <0x0 0x2300000 0x0 0x10000>;
+			interrupts = <0 36 0x4>; // Level high type
+			gpio-controller;
+			little-endian;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio1: gpio@2310000 {
+			compatible = "fsl,qoriq-gpio";
+			reg = <0x0 0x2310000 0x0 0x10000>;
+			interrupts = <0 36 0x4>; // Level high type
+			gpio-controller;
+			little-endian;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio2: gpio@2320000 {
+			compatible = "fsl,qoriq-gpio";
+			reg = <0x0 0x2320000 0x0 0x10000>;
+			interrupts = <0 37 0x4>; // Level high type
+			gpio-controller;
+			little-endian;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+		gpio3: gpio@2330000 {
+			compatible = "fsl,qoriq-gpio";
+			reg = <0x0 0x2330000 0x0 0x10000>;
+			interrupts = <0 37 0x4>; // Level high type
+			gpio-controller;
+			little-endian;
+			#gpio-cells = <2>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+		};
+
+
+		i2c0: i2c@2000000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2000000 0x0 0x10000>;
+			interrupts = <0 34 0x4>; // Level high type
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			fsl-scl-gpio = <&gpio2 15 0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@2010000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2010000 0x0 0x10000>;
+			interrupts = <0 34 0x4>; // Level high type
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@2020000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2020000 0x0 0x10000>;
+			interrupts = <0 35 0x4>; // Level high type
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@2030000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2030000 0x0 0x10000>;
+			interrupts = <0 35 0x4>; // Level high type
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@2040000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2040000 0x0 0x10000>;
+			interrupts = <0 74 0x4>; // Level high type
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			fsl-scl-gpio = <&gpio2 16 0>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@2050000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2050000 0x0 0x10000>;
+			interrupts = <0 74 0x4>; // Level high type
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@2060000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2060000 0x0 0x10000>;
+			interrupts = <0 75 0x4>; // Level high type
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			status = "disabled";
+		};
+
+		i2c7: i2c@2070000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2070000 0x0 0x10000>;
+			interrupts = <0 75 0x4>; // Level high type
+			clock-names = "i2c";
+			clocks = <&clockgen 4 7>;
+			status = "disabled";
+		};
+
+		uart0: serial@21c0000 {
+			device_type = "serial";
+			compatible = "arm,pl011","arm,sbsa-uart";
+			reg = <0x0 0x21c0000 0x0 0x1000>;
+			interrupts = <0 32 0x4>;	// Level high type
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		uart1: serial@21d0000 {
+			device_type = "serial";
+			compatible = "arm,pl011","arm,sbsa-uart";
+			reg = <0x0 0x21d0000 0x0 0x1000>;
+			interrupts = <0 33 0x4>;	// Level high type
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		uart2: serial@21e0000 {
+			device_type = "serial";
+			compatible = "arm,pl011","arm,sbsa-uart";
+			reg = <0x0 0x21e0000 0x0 0x1000>;
+			interrupts = <0 72 0x4>;	// Level high type
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		uart3: serial@21f0000 {
+			device_type = "serial";
+			compatible = "arm,pl011","arm,sbsa-uart";
+			reg = <0x0 0x21f0000 0x0 0x1000>;
+			interrupts = <0 73 0x4>;	// Level high type
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		smmu: iommu@5000000 {
+			compatible = "arm,mmu-500";
+			reg = <0 0x5000000 0 0x800000>;
+			#iommu-cells = <1>;
+			#global-interrupts = <14>;
+			interrupts = <0 13 4>, // global secure fault
+				     <0 14 4>, // combined secure interrupt
+				     <0 15 4>, // global non-secure fault
+				     <0 16 4>, // combined non-secure interrupt
+				// performance counter interrupts 0-9
+				     <0 211 4>, <0 212 4>,
+				     <0 213 4>, <0 214 4>,
+				     <0 215 4>, <0 216 4>,
+				     <0 217 4>, <0 218 4>,
+				     <0 219 4>, <0 220 4>,
+				// per context interrupt, 64 interrupts
+				     <0 146 4>, <0 147 4>,
+				     <0 148 4>, <0 149 4>,
+				     <0 150 4>, <0 151 4>,
+				     <0 152 4>, <0 153 4>,
+				     <0 154 4>, <0 155 4>,
+				     <0 156 4>, <0 157 4>,
+				     <0 158 4>, <0 159 4>,
+				     <0 160 4>, <0 161 4>,
+				     <0 162 4>, <0 163 4>,
+				     <0 164 4>, <0 165 4>,
+				     <0 166 4>, <0 167 4>,
+				     <0 168 4>, <0 169 4>,
+				     <0 170 4>, <0 171 4>,
+				     <0 172 4>, <0 173 4>,
+				     <0 174 4>, <0 175 4>,
+				     <0 176 4>, <0 177 4>,
+				     <0 178 4>, <0 179 4>,
+				     <0 180 4>, <0 181 4>,
+				     <0 182 4>, <0 183 4>,
+				     <0 184 4>, <0 185 4>,
+				     <0 186 4>, <0 187 4>,
+				     <0 188 4>, <0 189 4>,
+				     <0 190 4>, <0 191 4>,
+				     <0 192 4>, <0 193 4>,
+				     <0 194 4>, <0 195 4>,
+				     <0 196 4>, <0 197 4>,
+				     <0 198 4>, <0 199 4>,
+				     <0 200 4>, <0 201 4>,
+				     <0 202 4>, <0 203 4>,
+				     <0 204 4>, <0 205 4>,
+				     <0 206 4>, <0 207 4>,
+				     <0 208 4>, <0 209 4>;
+			dma-coherent;
+		};
+
+		usb0: usb3@3100000 {
+			status = "disabled";
+			compatible = "snps,dwc3";
+			reg = <0x0 0x3100000 0x0 0x10000>;
+			interrupts = <0 80 0x4>; // Level high type
+			dr_mode = "host";
+			snps,quirk-frame-length-adjustment = <0x20>;
+			snps,dis_rxdet_inp3_quirk;
+		};
+
+		usb1: usb3@3110000 {
+			status = "disabled";
+			compatible = "snps,dwc3";
+			reg = <0x0 0x3110000 0x0 0x10000>;
+			interrupts = <0 81 0x4>; // Level high type
+			dr_mode = "host";
+			snps,quirk-frame-length-adjustment = <0x20>;
+			snps,dis_rxdet_inp3_quirk;
+		};
+
+		watchdog@23a0000 {
+			compatible = "arm,sbsa-gwdt";
+			reg = <0x0 0x23a0000 0 0x1000>,
+			      <0x0 0x2390000 0 0x1000>;
+			interrupts = <0 59 4>;
+			timeout-sec = <30>;
+		};
+
+	};
+};
-- 
2.7.4

Re: [PATCH 4/5] arm64: dts: add QorIQ LX2160A SoC support

[Sudeep Holla]

On Mon, Aug 20, 2018 at 12:17:15PM +0530, Vabhav Sharma wrote:
> LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
> 
> LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores
> in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C
> controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA
> UARTs etc.
> 
> Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
> Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
> Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 572 +++++++++++++++++++++++++
>  1 file changed, 572 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> 
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> new file mode 100644
> index 0000000..e35e494
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> @@ -0,0 +1,572 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Device Tree Include file for Layerscape-LX2160A family SoC.
> +//
> +// Copyright 2018 NXP
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/memreserve/ 0x80000000 0x00010000;
> +
> +/ {
> +	compatible = "fsl,lx2160a";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		// 8 clusters having 2 Cortex-A72 cores each
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a72";
> +			reg = <0x0>;
> +			clocks = <&clockgen 1 0>;
> +			next-level-cache = <&cluster0_l2>;

If you expect to get cache properties in sysfs entries, you need to populate
them here and for each L2 cache.

[...]

> +
> +	rstcr: syscon@1e60000 {
> +		compatible = "syscon";
> +		reg = <0x0 0x1e60000 0x0 0x4>;
> +	};
> +
> +	reboot {
> +		compatible ="syscon-reboot";
> +		regmap = <&rstcr>;
> +		offset = <0x0>;
> +		mask = <0x2>;

Is this disabled in bootloader ? With PSCI, it's preferred to use
SYSTEM_RESET/OFF. EL3 f/w may need to do some housekeeping on poweroff.

> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <1 13 4>, // Physical Secure PPI, active-low

The comment says active low but the value 4 indicates it's HIGH from
"include/dt-bindings/interrupt-controller/irq.h"

> +			     <1 14 4>, // Physical Non-Secure PPI, active-low
> +			     <1 11 4>, // Virtual PPI, active-low
> +			     <1 10 4>; // Hypervisor PPI, active-low
> +	};
> +
> +	pmu {
> +		compatible = "arm,armv8-pmuv3";

More specific compatible preferably "arm,cortex-a72-pmu" ?

--
Regards,
Sudeep

RE: [PATCH 4/5] arm64: dts: add QorIQ LX2160A SoC support

[Vabhav Sharma]

> -----Original Message-----
> From: Sudeep Holla <sudeep.holla@arm.com>
> Sent: Tuesday, August 21, 2018 3:47 PM
> To: Vabhav Sharma <vabhav.sharma@nxp.com>
> Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> robh+dt@kernel.org; mark.rutland@arm.com; linuxppc-dev@lists.ozlabs.org;
> linux-arm-kernel@lists.infradead.org; mturquette@baylibre.com;
> sboyd@kernel.org; rjw@rjwysocki.net; viresh.kumar@linaro.org; linux-
> clk@vger.kernel.org; linux-pm@vger.kernel.org; linux-kernel-
> owner@vger.kernel.org; catalin.marinas@arm.com; will.deacon@arm.com;
> gregkh@linuxfoundation.org; arnd@arndb.de;
> kstewart@linuxfoundation.org; yamada.masahiro@socionext.com;
> linux@armlinux.org.uk; Varun Sethi <V.Sethi@nxp.com>; Udit Kumar
> <udit.kumar@nxp.com>; Ramneek Mehresh <ramneek.mehresh@nxp.com>;
> Ying Zhang <ying.zhang22455@nxp.com>; Nipun Gupta
> <nipun.gupta@nxp.com>; Priyanka Jain <priyanka.jain@nxp.com>; Yogesh
> Narayan Gaur <yogeshnarayan.gaur@nxp.com>; Sriram Dash
> <sriram.dash@nxp.com>; Sudeep Holla <sudeep.holla@arm.com>
> Subject: Re: [PATCH 4/5] arm64: dts: add QorIQ LX2160A SoC support
> 
> On Mon, Aug 20, 2018 at 12:17:15PM +0530, Vabhav Sharma wrote:
> > LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture.
> >
> > LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor
> > cores in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8
> > I2C controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011
> > SBSA UARTs etc.
> >
> > Signed-off-by: Ramneek Mehresh <ramneek.mehresh@nxp.com>
> > Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
> > Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
> > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
> > Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 572
> > +++++++++++++++++++++++++
> >  1 file changed, 572 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > new file mode 100644
> > index 0000000..e35e494
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> > @@ -0,0 +1,572 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Device Tree
> > +Include file for Layerscape-LX2160A family SoC.
> > +//
> > +// Copyright 2018 NXP
> > +
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/memreserve/ 0x80000000 0x00010000;
> > +
> > +/ {
> > +	compatible = "fsl,lx2160a";
> > +	interrupt-parent = <&gic>;
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		// 8 clusters having 2 Cortex-A72 cores each
> > +		cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a72";
> > +			reg = <0x0>;
> > +			clocks = <&clockgen 1 0>;
> > +			next-level-cache = <&cluster0_l2>;
> 
> If you expect to get cache properties in sysfs entries, you need to populate
> them here and for each L2 cache.
Rather sysfs, If Entry is not present then print  "cacheinfo: Unable to detect cache hierarchy for CPU 0" appears in boot log which is bad saying something is not present.
Either this print is require change to debug instead of warning.
> 
> [...]
> 
> > +
> > +	rstcr: syscon@1e60000 {
> > +		compatible = "syscon";
> > +		reg = <0x0 0x1e60000 0x0 0x4>;
> > +	};
> > +
> > +	reboot {
> > +		compatible ="syscon-reboot";
> > +		regmap = <&rstcr>;
> > +		offset = <0x0>;
> > +		mask = <0x2>;
> 
> Is this disabled in bootloader ? With PSCI, it's preferred to use
> SYSTEM_RESET/OFF. EL3 f/w may need to do some housekeeping on
> poweroff.
No, PSCIv0.2 is used and control passes to EL3 fw via smc call, psci node is present in the file.
This node is not required and keeping it in case PSCI is not used.
> 
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv8-timer";
> > +		interrupts = <1 13 4>, // Physical Secure PPI, active-low
> 
> The comment says active low but the value 4 indicates it's HIGH from
> "include/dt-bindings/interrupt-controller/irq.h"
Thanks, I will change the entries to existing definition IRQ_TYPE_LEVEL_LOW,GIC_PPI which is self-explanatory and not require comments
> 
> > +			     <1 14 4>, // Physical Non-Secure PPI, active-low
> > +			     <1 11 4>, // Virtual PPI, active-low
> > +			     <1 10 4>; // Hypervisor PPI, active-low
> > +	};
> > +
> > +	pmu {
> > +		compatible = "arm,armv8-pmuv3";
> 
> More specific compatible preferably "arm,cortex-a72-pmu" ?
Sure.
> 
> --
> Regards,
> Sudeep

[PATCH 5/5] arm64: dts: add LX2160ARDB board support

[Vabhav Sharma]

LX2160A reference design board (RDB) is a high-performance
computing, evaluation, and development platform with LX2160A
SoC.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
---
 arch/arm64/boot/dts/freescale/Makefile            |  1 +
 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 95 +++++++++++++++++++++++
 2 files changed, 96 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 86e18ad..445b72b 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
new file mode 100644
index 0000000..70fad20
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree file for LX2160ARDB
+//
+// Copyright 2018 NXP
+
+/dts-v1/;
+
+#include "fsl-lx2160a.dtsi"
+
+/ {
+	model = "NXP Layerscape LX2160ARDB";
+	compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
+
+	aliases {
+		crypto = &crypto;
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;
+		serial3 = &uart3;
+	};
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	pca9547@77 {
+		compatible = "nxp,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+
+			ina220@40 {
+				compatible = "ti,ina220";
+				reg = <0x40>;
+				shunt-resistor = <1000>;
+			};
+		};
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			sa56004@4c {
+				compatible = "nxp,sa56004";
+				reg = <0x4c>;
+			};
+
+			sa56004@4d {
+				compatible = "nxp,sa56004";
+				reg = <0x4d>;
+			};
+		};
+	};
+};
+
+&i2c4 {
+	status = "okay";
+
+	rtc@51 {
+		compatible = "nxp,pcf2129";
+		reg = <0x51>;
+		// IRQ10_B
+		interrupts = <0 150 0x4>;
+		};
+
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&crypto {
+	status = "okay";
+};
-- 
2.7.4

Re: [PATCH 5/5] arm64: dts: add LX2160ARDB board support

[Rob Herring]

On Mon, Aug 20, 2018 at 1:52 PM Vabhav Sharma <vabhav.sharma@nxp.com> wrote:
>
> LX2160A reference design board (RDB) is a high-performance
> computing, evaluation, and development platform with LX2160A
> SoC.
>
> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/Makefile            |  1 +
>  arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 95 +++++++++++++++++++++++
>  2 files changed, 96 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 86e18ad..445b72b 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> new file mode 100644
> index 0000000..70fad20
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +//
> +// Device Tree file for LX2160ARDB
> +//
> +// Copyright 2018 NXP
> +
> +/dts-v1/;
> +
> +#include "fsl-lx2160a.dtsi"
> +
> +/ {
> +       model = "NXP Layerscape LX2160ARDB";
> +       compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
> +
> +       aliases {
> +               crypto = &crypto;

Drop this. Aliases should be numbered, and this is not a standard
alias name either.

> +               serial0 = &uart0;
> +               serial1 = &uart1;
> +               serial2 = &uart2;
> +               serial3 = &uart3;
> +       };
> +       chosen {
> +               stdout-path = "serial0:115200n8";
> +       };
> +};
> +
> +&uart0 {
> +       status = "okay";
> +};
> +
> +&uart1 {
> +       status = "okay";
> +};
> +
> +&i2c0 {
> +       status = "okay";
> +       pca9547@77 {

i2c-mux@77

> +               compatible = "nxp,pca9547";
> +               reg = <0x77>;
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               i2c@2 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x2>;
> +
> +                       ina220@40 {
> +                               compatible = "ti,ina220";
> +                               reg = <0x40>;
> +                               shunt-resistor = <1000>;
> +                       };
> +               };
> +
> +               i2c@3 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x3>;
> +
> +                       sa56004@4c {

temperature-sensor@4c

> +                               compatible = "nxp,sa56004";
> +                               reg = <0x4c>;
> +                       };
> +
> +                       sa56004@4d {
> +                               compatible = "nxp,sa56004";
> +                               reg = <0x4d>;
> +                       };
> +               };
> +       };
> +};
> +
> +&i2c4 {
> +       status = "okay";
> +
> +       rtc@51 {
> +               compatible = "nxp,pcf2129";
> +               reg = <0x51>;
> +               // IRQ10_B
> +               interrupts = <0 150 0x4>;
> +               };
> +
> +};
> +
> +&usb0 {
> +       status = "okay";
> +};
> +
> +&usb1 {
> +       status = "okay";
> +};
> +
> +&crypto {
> +       status = "okay";
> +};
> --
> 2.7.4
>

RE: [PATCH 5/5] arm64: dts: add LX2160ARDB board support

[Vabhav Sharma]

> -----Original Message-----
> From: Rob Herring <robh+dt@kernel.org>
> Sent: Wednesday, August 22, 2018 2:15 AM
> To: Vabhav Sharma <vabhav.sharma@nxp.com>
> Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Mark Rutland
> <mark.rutland@arm.com>; linuxppc-dev <linuxppc-dev@lists.ozlabs.org>;
> moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE <linux-arm-
> kernel@lists.infradead.org>; Michael Turquette <mturquette@baylibre.com>;
> Stephen Boyd <sboyd@kernel.org>; Rafael J. Wysocki <rjw@rjwysocki.net>;
> Viresh Kumar <viresh.kumar@linaro.org>; linux-clk <linux-
> clk@vger.kernel.org>; open list:THERMAL <linux-pm@vger.kernel.org>; linux-
> kernel-owner@vger.kernel.org; Catalin Marinas <catalin.marinas@arm.com>;
> Will Deacon <will.deacon@arm.com>; Greg Kroah-Hartman
> <gregkh@linuxfoundation.org>; Arnd Bergmann <arnd@arndb.de>; Kate
> Stewart <kstewart@linuxfoundation.org>; Masahiro Yamada
> <yamada.masahiro@socionext.com>; Russell King <linux@armlinux.org.uk>;
> Varun Sethi <V.Sethi@nxp.com>; Udit Kumar <udit.kumar@nxp.com>;
> Priyanka Jain <priyanka.jain@nxp.com>; Sriram Dash
> <sriram.dash@nxp.com>
> Subject: Re: [PATCH 5/5] arm64: dts: add LX2160ARDB board support
> 
> On Mon, Aug 20, 2018 at 1:52 PM Vabhav Sharma
> <vabhav.sharma@nxp.com> wrote:
> >
> > LX2160A reference design board (RDB) is a high-performance computing,
> > evaluation, and development platform with LX2160A SoC.
> >
> > Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
> > Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
> > Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/Makefile            |  1 +
> >  arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 95
> > +++++++++++++++++++++++
> >  2 files changed, 96 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile
> > b/arch/arm64/boot/dts/freescale/Makefile
> > index 86e18ad..445b72b 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -13,3 +13,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-
> rdb.dtb
> >  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
> >  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
> >  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
> > +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > new file mode 100644
> > index 0000000..70fad20
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > @@ -0,0 +1,95 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) // // Device Tree file
> > +for LX2160ARDB // // Copyright 2018 NXP
> > +
> > +/dts-v1/;
> > +
> > +#include "fsl-lx2160a.dtsi"
> > +
> > +/ {
> > +       model = "NXP Layerscape LX2160ARDB";
> > +       compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
> > +
> > +       aliases {
> > +               crypto = &crypto;
> 
> Drop this. Aliases should be numbered, and this is not a standard alias name
> either.
Ok
> 
> > +               serial0 = &uart0;
> > +               serial1 = &uart1;
> > +               serial2 = &uart2;
> > +               serial3 = &uart3;
> > +       };
> > +       chosen {
> > +               stdout-path = "serial0:115200n8";
> > +       };
> > +};
> > +
> > +&uart0 {
> > +       status = "okay";
> > +};
> > +
> > +&uart1 {
> > +       status = "okay";
> > +};
> > +
> > +&i2c0 {
> > +       status = "okay";
> > +       pca9547@77 {
> 
> i2c-mux@77
Sure
> 
> > +               compatible = "nxp,pca9547";
> > +               reg = <0x77>;
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               i2c@2 {
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       reg = <0x2>;
> > +
> > +                       ina220@40 {
power-sensor@40
> > +                               compatible = "ti,ina220";
> > +                               reg = <0x40>;
> > +                               shunt-resistor = <1000>;
> > +                       };
> > +               };
> > +
> > +               i2c@3 {
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> > +                       reg = <0x3>;
> > +
> > +                       sa56004@4c {
> 
> temperature-sensor@4c
Ok, temperature-sensor-1@4c
> 
> > +                               compatible = "nxp,sa56004";
> > +                               reg = <0x4c>;
> > +                       };
> > +
> > +                       sa56004@4d {
Ok,temperature-sensor-2@4d
> > +                               compatible = "nxp,sa56004";
> > +                               reg = <0x4d>;
> > +                       };
> > +               };
> > +       };
> > +};
> > +
> > +&i2c4 {
> > +       status = "okay";
> > +
> > +       rtc@51 {
> > +               compatible = "nxp,pcf2129";
> > +               reg = <0x51>;
> > +               // IRQ10_B
> > +               interrupts = <0 150 0x4>;
> > +               };
> > +
> > +};
> > +
> > +&usb0 {
> > +       status = "okay";
> > +};
> > +
> > +&usb1 {
> > +       status = "okay";
> > +};
> > +
> > +&crypto {
> > +       status = "okay";
> > +};
> > --
> > 2.7.4
> >

Re: [PATCH 5/5] arm64: dts: add LX2160ARDB board support

[Rob Herring]

On Thu, Aug 23, 2018 at 10:08 AM Vabhav Sharma <vabhav.sharma@nxp.com> wrote:

[...]

> > > +               i2c@3 {
> > > +                       #address-cells = <1>;
> > > +                       #size-cells = <0>;
> > > +                       reg = <0x3>;
> > > +
> > > +                       sa56004@4c {
> >
> > temperature-sensor@4c
> Ok, temperature-sensor-1@4c

No, that's not what I said. You don't need the '-1' because the
unit-address makes the node name unique. Node names are supposed to be
generic based on the class/type of device. See the DT spec.

> >
> > > +                               compatible = "nxp,sa56004";
> > > +                               reg = <0x4c>;
> > > +                       };
> > > +
> > > +                       sa56004@4d {
> Ok,temperature-sensor-2@4d
> > > +                               compatible = "nxp,sa56004";
> > > +                               reg = <0x4d>;
> > > +                       };
> > > +               };
> > > +       };
> > > +};
> > > +
> > > +&i2c4 {
> > > +       status = "okay";
> > > +
> > > +       rtc@51 {
> > > +               compatible = "nxp,pcf2129";
> > > +               reg = <0x51>;
> > > +               // IRQ10_B
> > > +               interrupts = <0 150 0x4>;
> > > +               };
> > > +
> > > +};
> > > +
> > > +&usb0 {
> > > +       status = "okay";
> > > +};
> > > +
> > > +&usb1 {
> > > +       status = "okay";
> > > +};
> > > +
> > > +&crypto {
> > > +       status = "okay";
> > > +};
> > > --
> > > 2.7.4
> > >

Re: [PATCH 5/5] arm64: dts: add LX2160ARDB board support

[Scott Wood]

On Tue, 2018-08-21 at 15:45 -0500, Rob Herring wrote:
> On Mon, Aug 20, 2018 at 1:52 PM Vabhav Sharma <vabhav.sharma@nxp.com> wrote:
> > +/ {
> > +       model = "NXP Layerscape LX2160ARDB";
> > +       compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
> > +
> > +       aliases {
> > +               crypto = &crypto;
> 
> Drop this. Aliases should be numbered, and this is not a standard
> alias name either.

Is this a new rule?  In any case, U-Boot looks for a "crypto" alias.

-Scott

Re: [PATCH 5/5] arm64: dts: add LX2160ARDB board support

[Horia Geanta]

On 8/29/2018 3:31 AM, Scott Wood wrote:
> On Tue, 2018-08-21 at 15:45 -0500, Rob Herring wrote:
>> On Mon, Aug 20, 2018 at 1:52 PM Vabhav Sharma <vabhav.sharma@nxp.com> wrote:
>>> +/ {
>>> +       model = "NXP Layerscape LX2160ARDB";
>>> +       compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
>>> +
>>> +       aliases {
>>> +               crypto = &crypto;
>>
>> Drop this. Aliases should be numbered, and this is not a standard
>> alias name either.
> 
> Is this a new rule?  In any case, U-Boot looks for a "crypto" alias.
> 
(Replying here, I did not see a follow-up).

Indeed, U-boot relies on the "crypto" alias.
This is true for all SoCs with CAAM crypto engine, a pretty lengthy list.

Could you please clarify?
Also: Is numbering needed even when there is a single instance of the block?

Looking at a recent discussion
https://lore.kernel.org/patchwork/patch/991718
I see the proposal is for the ID to be optional:
> Alias names are often suffixed with a numeric ID, especially when there may
> be multiple instances of the same type. The ID typically corresponds to the
[...]

Thanks,
Horia