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Thu, 08 Oct 2026 21:06:38 -0700 (PDT) X-Received: by 2002:a17:90a:d006:b0:3a8:6a04:80ef with SMTP id 98e67ed59e1d1-3ab3a2901c2mr662396a91.6.1791518798366; Thu, 08 Oct 2026 21:06:38 -0700 (PDT) Received: from [192.168.1.6] ([117.143.161.217]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ab37139b59sm1611384a91.13.2026.10.08.21.06.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Oct 2026 21:06:37 -0700 (PDT) Message-ID: Date: Fri, 9 Oct 2026 12:06:29 +0800 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v19 11/12] arm64: dts: qcom: kaanapali: Add CCI controller nodes To: Loic Poulain Cc: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa , linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati References: <20261008-kaanapali-camss-v19-0-b2c583ef50e0@oss.qualcomm.com> <20261008-kaanapali-camss-v19-11-b2c583ef50e0@oss.qualcomm.com> Content-Language: en-US From: Hangxiang Ma In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: HyjqLUA0Vn9gcIpalmtFDc4IU3PGWf4W X-Authority-Analysis: v=2.4 cv=csYOAF4i c=1 sm=1 tr=0 ts=6ac8684f cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=K/RrOd38U9TixX+j9hIN8g==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=GUC6nXMZ9ruFzsaAOnwA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA5MDAxNiBTYWx0ZWRfX7aLCt3jYpLQZ jTpCUNaXrJlH5rlhZOoIpQj3Aoox9JV1NKaiCyoYlCz4yArMZ+33AeisLWZpVynnYrX4ZuKeDrb Y/JBy4brQdXbRUC2Z62Ma/XgBrbMJBBhOK3RI/5iGfBKVYT1egxJJtTh+NVKqBjXIZfEkeAuygx mfI2/imQ/giqfsa8WzJsvmGdYgn9evyRuxdRlwMXiWdAXnvmPpfeBjk7o+/m+kfjz1rMulv3tM7 wyUFOSYDNO9VqU62d3hJpGLVInG90vG2Ydej8e0Iz5xuPjl23P09NUUlSumBH96DmNNtz/j0c+u Gcbs0L43v+xlNR9bAOA5KFC2oAToi1FDp72ahn1KITzXbqB/QO72cMAh5QKeGizqzlwXXepI6ZK rWGxQBx1c4ADsYbsN9GNZN89h2NO7tyHz+NIDzOgA/sLYMQ5oC+PvNqEdsp+MsV5nzcjOEqOfEw n96EAxBRYOodiRpUQlQ== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA5MDAxNiBTYWx0ZWRfX1ScjFdCS4a1z EwYUitCQJdztbQmtav54NQCw/C5XVAZjVZppJwQZzXX1VtGO/UbA8GT1vhW0ez/1AHUxgtc60QS 8ZJydFudMusUH3ik16nDWDLa9OhyV4U= X-Proofpoint-GUID: HyjqLUA0Vn9gcIpalmtFDc4IU3PGWf4W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-09_02,2026-10-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610090016 On 10/9/2026 12:16 AM, Loic Poulain wrote: > On Thu, Oct 8, 2026 at 9:14 AM Hangxiang Ma > wrote: >> >> Add the three Camera Control Interface (CCI) controllers present on the >> Kaanapali SoC. Each controller provides two I2C hosts used for camera >> sensor control, so define the controller nodes and their pinctrl states. >> >> The first bus has two CCI bus master pinouts: >> cci_i2c_sda0 = gpio109 >> cci_i2c_scl0 = gpio110 >> >> cci_i2c_sda1 = gpio111 >> cci_i2c_scl1 = gpio112 >> >> The second bus has two CCI bus master pinouts: >> cci_i2c_sda3 = gpio113 >> cci_i2c_scl3 = gpio114 >> >> cci_i2c_sda4 = gpio107 >> cci_i2c_scl4 = gpio160 >> >> The third bus has two CCI bus master pinouts: >> cci_i2c_sda5 = gpio108 >> cci_i2c_scl5 = gpio149 >> >> cci_i2c_sda6 = gpio115 >> cci_i2c_scl6 = gpio116 >> >> Reviewed-by: Vladimir Zapolskiy >> Signed-off-by: Hangxiang Ma >> --- >> arch/arm64/boot/dts/qcom/kaanapali.dtsi | 303 ++++++++++++++++++++++++++++++++ >> 1 file changed, 303 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi >> index 7e5106865e7e..710af0597aaa 100644 >> --- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi >> +++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi >> @@ -3749,6 +3749,117 @@ port@5 { >> }; >> }; >> >> + cci0: cci@941b000 { >> + compatible = "qcom,kaanapali-cci", "qcom,msm8996-cci"; >> + reg = <0x0 0x0941b000 0x0 0x1000>; >> + >> + interrupts = ; >> + >> + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>, >> + <&camcc CAM_CC_CCI_0_CLK>; >> + clock-names = "ahb", >> + "cci"; >> + >> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; >> + >> + pinctrl-0 = <&cci0_i2c0_default &cci0_i2c1_default>; >> + pinctrl-1 = <&cci0_i2c0_sleep &cci0_i2c1_sleep>; >> + pinctrl-names = "default", "sleep"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + >> + cci0_i2c0: i2c-bus@0 { >> + reg = <0>; >> + clock-frequency = <1000000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + >> + cci0_i2c1: i2c-bus@1 { >> + reg = <1>; >> + clock-frequency = <1000000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + }; >> + >> + cci1: cci@941c000 { >> + compatible = "qcom,kaanapali-cci", "qcom,msm8996-cci"; >> + reg = <0x0 0x0941c000 0x0 0x1000>; >> + >> + interrupts = ; >> + >> + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>, >> + <&camcc CAM_CC_CCI_1_CLK>; >> + clock-names = "ahb", >> + "cci"; >> + >> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; >> + >> + pinctrl-0 = <&cci1_i2c0_default &cci1_i2c1_default>; >> + pinctrl-1 = <&cci1_i2c0_sleep &cci1_i2c1_sleep>; >> + pinctrl-names = "default", "sleep"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + >> + cci1_i2c0: i2c-bus@0 { >> + reg = <0>; >> + clock-frequency = <1000000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + >> + cci1_i2c1: i2c-bus@1 { >> + reg = <1>; >> + clock-frequency = <1000000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + }; >> + >> + cci2: cci@941d000 { >> + compatible = "qcom,kaanapali-cci", "qcom,msm8996-cci"; >> + reg = <0x0 0x0941d000 0x0 0x1000>; >> + >> + interrupts = ; >> + >> + clocks = <&camcc CAM_CC_CAM_TOP_AHB_CLK>, >> + <&camcc CAM_CC_CCI_2_CLK>; >> + clock-names = "ahb", >> + "cci"; >> + >> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; >> + >> + pinctrl-0 = <&cci2_i2c0_default &cci2_i2c1_default>; >> + pinctrl-1 = <&cci2_i2c0_sleep &cci2_i2c1_sleep>; >> + pinctrl-names = "default", "sleep"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + >> + cci2_i2c0: i2c-bus@0 { >> + reg = <0>; >> + clock-frequency = <1000000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + >> + cci2_i2c1: i2c-bus@1 { >> + reg = <1>; >> + clock-frequency = <1000000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + }; >> + >> csiphy0: phy@9523000 { >> compatible = "qcom,kaanapali-csi2-phy"; >> reg = <0x0 0x09523000 0x0 0x2000>; >> @@ -4459,6 +4570,198 @@ tlmm: pinctrl@f100000 { >> #interrupt-cells = <2>; >> wakeup-parent = <&pdc>; >> >> + cci0_i2c0_default: cci0-i2c0-default-state { >> + scl-pins { >> + pins = "gpio110"; >> + function = "cci_i2c_scl"; >> + drive-strength = <2>; >> + bias-pull-up; > > A general comment on the CCI DTS patches: why are the pull-ups enabled > here (for SCL/SDA)? Do we expect boards to lack the external pull-ups > required by I²C? If not, enabling the internal pull-ups seems > unnecessary. Also, what is their effective resistance on these > platforms? Aren't they typically too weak to meet the rise-time > requirements of most I²C modes anyway? > Thanks for pointing this out. The CCI buses are expected to have the required external pull-up resistors on the board. In fact, the above properties follow the established Qualcomm CCI pinctrl configuration used by other chipsets and platforms, as well as the downstream Kaanapali DTS. I checked the Kaanapali pinctrl driver. Its CCI GPIO groups do not define an i2c_pull_bit, so bias-pull-up would silently fall back to the normal weak pull-up. I will therefore change the CCI default states to bias-disable instead of relying on the internal pull-up. The required I2C pull-ups should be provided at board level; the existing sleep-state pull-down configuration will remain unchanged. --- Best Regards, Hangxiang