From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.0 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58A70C4724C for ; Fri, 1 May 2020 08:08:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33874208C3 for ; Fri, 1 May 2020 08:08:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (1024-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="wrzAS/Ue" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728348AbgEAIIL (ORCPT ); Fri, 1 May 2020 04:08:11 -0400 Received: from mail26.static.mailgun.info ([104.130.122.26]:42920 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726452AbgEAIIK (ORCPT ); Fri, 1 May 2020 04:08:10 -0400 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1588320489; h=Content-Transfer-Encoding: Content-Type: In-Reply-To: MIME-Version: Date: Message-ID: From: References: To: Subject: Sender; bh=qcrL4Oy4sFTZZxhYPssgoqySFm5x5kTnylNldDFq1lo=; b=wrzAS/UettdXBW5kQIUCQkgkv5+7T0hQk234K7Hpq36PMeqbP4ebNgSDz8Dyo0Wwon9omunB bxQw3gsbFvHacwUHFgOwM4a/sTS/G4XNhPQYZGnpdVmd1J6ZNE9g5hl1Tzrj4vge+mKQDUBD U/SbfHHTnjOZYVyi5E/OJ3AC4bg= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI1YmJiNiIsICJkZXZpY2V0cmVlQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5eabd8e7.7f4fad3efc00-smtp-out-n03; Fri, 01 May 2020 08:08:07 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 9F8E0C432C2; Fri, 1 May 2020 08:08:06 +0000 (UTC) Received: from [192.168.1.227] (unknown [49.204.180.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty) by smtp.codeaurora.org (Postfix) with ESMTPSA id C2FB1C433CB; Fri, 1 May 2020 08:08:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org C2FB1C433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org Subject: Re: [Freedreno] [PATCH v2] dt-bindings: arm-smmu: Add sc7180 compatible string and mem_iface clock To: Doug Anderson , freedreno , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , dri-devel@freedesktop.org, linux-arm-msm , LKML , Matthias Kaehlcke , Rob Herring , Robin Murphy , Sai Prakash Ranjan References: <1588219187-19295-1-git-send-email-smasetty@codeaurora.org> <20200430181233.GA21991@jcrouse1-lnx.qualcomm.com> From: Sharat Masetty Message-ID: Date: Fri, 1 May 2020 13:38:00 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.6.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 4/30/2020 11:51 PM, Doug Anderson wrote: > Hi, > > On Thu, Apr 30, 2020 at 11:12 AM Jordan Crouse wrote: >> On Thu, Apr 30, 2020 at 09:29:47AM +0530, Sharat Masetty wrote: >>> This patch adds a new compatible string for sc7180 and also an >>> additional clock listing needed to power the TBUs and the TCU. >>> >>> Signed-off-by: Sharat Masetty >>> --- >>> v2: Addressed review comments from Doug >>> >>> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 8 ++++++++ >>> 1 file changed, 8 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >>> index 6515dbe..ba5dba4 100644 >>> --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >>> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml >>> @@ -28,6 +28,7 @@ properties: >>> - enum: >>> - qcom,msm8996-smmu-v2 >>> - qcom,msm8998-smmu-v2 >>> + - qcom,sc7180-smmu-v2 >>> - qcom,sdm845-smmu-v2 >>> - const: qcom,smmu-v2 >>> >>> @@ -113,16 +114,23 @@ properties: >>> present in such cases. >>> >>> clock-names: >>> + minItems: 2 >>> + maxItems: 3 >>> items: >>> - const: bus >>> - const: iface >>> + - const: mem_iface >> Hi Sharat - >> >> I think there was a bit of confusion due to renaming between downstream and >> upstream. Currently for the sdm845 and friends we have: >> >> clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, >> <&gcc GCC_GPU_CFG_AHB_CLK>; >> clock-names = "bus", "iface"; >> >> Confusingly these same clocks downstream are "mem_iface_clk" and "iface_clk" >> respectively. >> >> It looks like you are trying to add GCC_DDRSS_GPU_AXI_CLK as "mem_iface" which >> was formerly "mem_clk" downstream. I'm not sure if the naming change is >> intentional or you were trying to make upstream and downstream match and didn't >> realize that they were renamed. >> >> I'm not sure if we need DDRSS_GPU_AXI_CLK or not. Empirically it works without >> it for sdm845 (I don't have a sc7180 to test) but we should probably loop back >> with either the clock team or the hardware designers to be sure there isn't a >> corner case that is missing. I agree with Doug that its always best if we don't >> need to add a clock. Thanks Jordan and Doug for the updates. My intention was to add the third clock as listed downstream, but as you said the naming is a bit misleading. From the clock GCC_DDRSS_GPU_AXI_CLK description, this is needed for the GPU to DDR access and all transactions to the DDR from the GPU go through the SMMU. It is listed in the SMMU dt node because its needed by SMMU to perform pagetable walks. I think we may be fine by not listing this clock in the SMMU node because the same clock is listed in both the GMU and also the GPU. > I can confirm that on sc7180 the GPU seems to come up just fine > without the clock being specified in the iommu node. Definitely would > be good to know what's broken and if nothing is broken maybe we can > change this patch to just add the sc7180 compatible string and drop > the clock. I do note that the GMU already has a reference to the same > "GCC_DDRSS_GPU_AXI_CLK" clock. > > -Doug > _______________________________________________ > Freedreno mailing list > Freedreno@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/freedreno