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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae0a1505294sm32885366b.83.2025.06.23.07.09.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Jun 2025 07:09:32 -0700 (PDT) Message-ID: Date: Mon, 23 Jun 2025 16:09:30 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 1/2] arm64: dts: qcom: Add eMMC support for qcs8300 To: Sayali Lokhande , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250619070224.23428-1-quic_sayalil@quicinc.com> <20250619070224.23428-2-quic_sayalil@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250619070224.23428-2-quic_sayalil@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: a__eStK8YNCmHSTeNmD9FZQqG8sjtPwo X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIzMDA4NCBTYWx0ZWRfX0rRFEw4Y4hRl z2qvEoRt4FjfjZa+mysMEVl84DuLC/YsNkiyp9tE/vtNbBdAuoNFVWBw4AsTtEmx7rGVcAbNN1a 00uahKr2bHHhv6CnwDT4RZ1GjH4l7zZJCPCK44gXTOpb8nOMGlSRqNUmPumYXMCRlpdJXbuAv61 F2AODUP6rL//JU7ckTsU2hhBMRGFM4fi85WK+9FeJl/ntghjBL2o/m39P2qkDljUh8ucbUWktHa JRBQ4gt+6Kq8ZDVXD42BElkhRJviWB/EGnHqa0EG08EHMRkXTiDfqgWYowLw8V8yAFw5YwCditV 5/6WHKsL04DPYaupQi8HEofNj+OqB93o43P2FdemoP554c4TUqnPqZbLdRDMIL1MuTcrBF3pS70 0pIBuGO91mxYCZZOq/WooHOcwG3AXI1XQIGPDKOydYB/7gLIBLERldzHtpJepcngocfpvMZe X-Authority-Analysis: v=2.4 cv=caHSrmDM c=1 sm=1 tr=0 ts=68596020 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=COk6AnOGAAAA:8 a=ViSwFiuPWrUJpFAOtGMA:9 a=R9dU3JXcjent7X09:21 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: a__eStK8YNCmHSTeNmD9FZQqG8sjtPwo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-06-23_04,2025-06-23_05,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 lowpriorityscore=0 bulkscore=0 adultscore=0 mlxscore=0 spamscore=0 malwarescore=0 phishscore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506230084 On 6/19/25 9:02 AM, Sayali Lokhande wrote: > Add eMMC support for qcs8300 board. > > Signed-off-by: Sayali Lokhande > --- It's customary to split board and SoC changes into separate commits [...] > + sdhc_1: mmc@87C4000 { Please use lowercase hex across DT, in all places > + compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x0 0x87C4000 0x0 0x1000>, To make it easier to compare by eye, we tend to pad the address values to 8 hex digits with leading zeroes, please do so as well > + <0x0 0x87C5000 0x0 0x1000>; > + reg-names = "hc", > + "cqhci"; > + > + interrupts = , > + ; > + interrupt-names = "hc_irq", > + "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC1_AHB_CLK>, > + <&gcc GCC_SDCC1_APPS_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", > + "core", > + "xo"; > + > + resets = <&gcc GCC_SDCC1_BCR>; > + > + power-domains = <&rpmhpd RPMHPD_CX>; > + operating-points-v2 = <&sdhc1_opp_table>; > + iommus = <&apps_smmu 0x0 0x0>; In case anyone's wondering, this is actually the correct value > + interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; > + interconnect-names = "sdhc-ddr", > + "cpu-sdhc"; [...] > + sdc1_state_on: sdc1-on-state { > + clk-pins { > + pins = "sdc1_clk"; > + bias-disable; > + drive-strength = <16>; Please move bias properties under drive-strength for consistency > + }; > + > + cmd-pins { > + pins = "sdc1_cmd"; > + bias-pull-up; > + drive-strength = <10>; > + }; > + > + data-pins { > + pins = "sdc1_data"; > + bias-pull-up; > + drive-strength = <10>; > + }; > + > + rclk-pins { > + pins = "sdc1_rclk"; > + bias-pull-down; > + }; > + }; > + > + sdc1_state_off: sdc1-off-state { > + clk-pins { > + pins = "sdc1_clk"; > + bias-bus-hold; Is bus-hold what we want here? Other platforms do a pull-up/down or disable bias altogether Konrad