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[80.174.240.175]) by smtp.gmail.com with ESMTPSA id f2sm31416341wrq.34.2021.03.29.08.50.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Mar 2021 08:50:34 -0700 (PDT) Subject: Re: [PATCH 1/2] arm64: dts: mediatek: add MT6779 spi master dts node To: Mason Zhang , Rob Herring Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, hanks.chen@mediateka.com, wsd_upstream@mediatek.com References: <20210226105918.3057-1-Mason.Zhang@mediatek.com> From: Matthias Brugger Message-ID: Date: Mon, 29 Mar 2021 17:50:33 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210226105918.3057-1-Mason.Zhang@mediatek.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 26/02/2021 11:59, Mason Zhang wrote: > this patch add spi master dts node for mt6779 SOC. > > Signed-off-by: Mason Zhang > --- > arch/arm64/boot/dts/mediatek/mt6779.dtsi | 96 ++++++++++++++++++++++++ > 1 file changed, 96 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi > index 370f309d32de..ca72eb09cff9 100644 > --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi > @@ -219,6 +219,102 @@ > status = "disabled"; > }; > > + spi0: spi0@1100a000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + mediatek,pad-select = <0>; > + reg = <0 0x1100a000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI0>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; Please also update binding description accordingling and add as another patch. I wasn't able to find a 2/2 neither. I foudn v1 2/2 which on a quick look seemed the same as this patch. Regards, Matthias > + > + spi1: spi1@11010000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + mediatek,pad-select = <0>; > + reg = <0 0x11010000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI1>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi2: spi2@11012000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + mediatek,pad-select = <0>; > + reg = <0 0x11012000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI2>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi3: spi3@11013000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + mediatek,pad-select = <0>; > + reg = <0 0x11013000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI3>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi4: spi4@11018000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + mediatek,pad-select = <0>; > + reg = <0 0x11018000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI4>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi5: spi5@11019000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + mediatek,pad-select = <0>; > + reg = <0 0x11019000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI5>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi6: spi6@1101d000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + mediatek,pad-select = <0>; > + reg = <0 0x1101d000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI6>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi7: spi7@1101e000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + mediatek,pad-select = <0>; > + reg = <0 0x1101e000 0 0x1000>; > + interrupts = ; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI7>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > audio: clock-controller@11210000 { > compatible = "mediatek,mt6779-audio", "syscon"; > reg = <0 0x11210000 0 0x1000>; >