[PATCH v3 0/2] arm64: dts: socfpga: agilex5: add NAND daughter board

[PATCH v3 0/2] arm64: dts: socfpga: agilex5: add NAND daughter board

[niravkumar.l.rabara]

From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>

Agilex5 SoCFPGA devkit supports a separate NAND daughter board.
Document NAND daughter board compatible string and add board file.

Changes in v3:
  * Document Agilex5 NAND daughter board and use that compatible
    in the device tree.

link to v2:
 - https://lore.kernel.org/all/20250205101318.1778757-1-niravkumar.l.rabara@intel.com/

Changes in v2:
 * Use nand flash node name according to dt bindings to fix dt build warnings.
 * Arrange node in sequence.

link to v1:
 - https://lore.kernel.org/all/20250107084831.2750035-1-niravkumar.l.rabara@intel.com/

Niravkumar L Rabara (2):
  dt-bindings: intel: document Agilex5 NAND daughter board
  arm64: dts: socfpga: agilex5: add NAND daughter board

 .../bindings/arm/intel,socfpga.yaml           |  1 +
 arch/arm64/boot/dts/intel/Makefile            |  1 +
 .../dts/intel/socfpga_agilex5_socdk_nand.dts  | 89 +++++++++++++++++++
 3 files changed, 91 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts

-- 
2.25.1

[PATCH v3 1/2] dt-bindings: intel: document Agilex5 NAND daughter board

[niravkumar.l.rabara]

From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>

Agilex5 devkit supports a separate NAND daughter board.
Document Agilex5 NAND daughter board compatible.

Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
---
 Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
index 2ee0c740eb56..c75cd7d29f1a 100644
--- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
+++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
@@ -25,6 +25,7 @@ properties:
         items:
           - enum:
               - intel,socfpga-agilex5-socdk
+              - intel,socfpga-agilex5-socdk-nand
           - const: intel,socfpga-agilex5
 
 additionalProperties: true
-- 
2.25.1

[PATCH v3 2/2] arm64: dts: socfpga: agilex5: add NAND daughter board

[niravkumar.l.rabara]

From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>

The Agilex5 devkit supports a separate NAND daughter card.
The NAND daughter card replaces the SDMMC slot that is on the default
daughter card thus requires a separate board dts file.

Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
---
 arch/arm64/boot/dts/intel/Makefile            |  1 +
 .../dts/intel/socfpga_agilex5_socdk_nand.dts  | 89 +++++++++++++++++++
 2 files changed, 90 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts

diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index d39cfb723f5b..33f6d01266b1 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -3,5 +3,6 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
 				socfpga_agilex_socdk.dtb \
 				socfpga_agilex_socdk_nand.dtb \
 				socfpga_agilex5_socdk.dtb \
+				socfpga_agilex5_socdk_nand.dtb \
 				socfpga_n5x_socdk.dtb
 dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
new file mode 100644
index 000000000000..38a582ef86b4
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier:     GPL-2.0
+/*
+ * Copyright (C) 2025, Altera Corporation
+ */
+#include "socfpga_agilex5.dtsi"
+
+/ {
+	model = "SoCFPGA Agilex5 SoCDK NAND daughter board";
+	compatible = "intel,socfpga-agilex5-socdk-nand", "intel,socfpga-agilex5";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0 {
+			label = "hps_led0";
+			gpios = <&porta 6 GPIO_ACTIVE_HIGH>;
+		};
+
+		led1 {
+			label = "hps_led1";
+			gpios = <&porta 7 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the reg */
+		reg = <0x0 0x80000000 0x0 0x0>;
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i3c0 {
+	status = "okay";
+};
+
+&i3c1 {
+	status = "okay";
+};
+
+&nand {
+	status = "okay";
+
+	nand@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+		nand-bus-width = <8>;
+
+		partition@0 {
+			label = "u-boot";
+			reg = <0 0x200000>;
+		};
+		partition@200000 {
+			label = "root";
+			reg = <0x200000 0xffe00000>;
+		};
+	};
+};
+
+&osc1 {
+	clock-frequency = <25000000>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
-- 
2.25.1

Re: [PATCH v3 0/2] arm64: dts: socfpga: agilex5: add NAND daughter board

[Rob Herring (Arm)]

On Mon, 10 Feb 2025 15:46:02 +0800, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> 
> Agilex5 SoCFPGA devkit supports a separate NAND daughter board.
> Document NAND daughter board compatible string and add board file.
> 
> Changes in v3:
>   * Document Agilex5 NAND daughter board and use that compatible
>     in the device tree.
> 
> link to v2:
>  - https://lore.kernel.org/all/20250205101318.1778757-1-niravkumar.l.rabara@intel.com/
> 
> Changes in v2:
>  * Use nand flash node name according to dt bindings to fix dt build warnings.
>  * Arrange node in sequence.
> 
> link to v1:
>  - https://lore.kernel.org/all/20250107084831.2750035-1-niravkumar.l.rabara@intel.com/
> 
> Niravkumar L Rabara (2):
>   dt-bindings: intel: document Agilex5 NAND daughter board
>   arm64: dts: socfpga: agilex5: add NAND daughter board
> 
>  .../bindings/arm/intel,socfpga.yaml           |  1 +
>  arch/arm64/boot/dts/intel/Makefile            |  1 +
>  .../dts/intel/socfpga_agilex5_socdk_nand.dts  | 89 +++++++++++++++++++
>  3 files changed, 91 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
> 
> --
> 2.25.1
> 
> 
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/intel/' for 20250210074604.2410783-1-niravkumar.l.rabara@intel.com:

arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dtb: clock-controller@ffd10000: 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/clock/intel,easic-n5x.yaml#

Re: [PATCH v3 1/2] dt-bindings: intel: document Agilex5 NAND daughter board

[Krzysztof Kozlowski]

On Mon, Feb 10, 2025 at 03:46:03PM +0800, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> 
> Agilex5 devkit supports a separate NAND daughter board.
> Document Agilex5 NAND daughter board compatible.
> 
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> ---
>  Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 2/2] arm64: dts: socfpga: agilex5: add NAND daughter board

[Krzysztof Kozlowski]

On Mon, Feb 10, 2025 at 03:46:04PM +0800, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> 
> The Agilex5 devkit supports a separate NAND daughter card.
> The NAND daughter card replaces the SDMMC slot that is on the default
> daughter card thus requires a separate board dts file.
> 
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> ---
>  arch/arm64/boot/dts/intel/Makefile            |  1 +
>  .../dts/intel/socfpga_agilex5_socdk_nand.dts  | 89 +++++++++++++++++++
>  2 files changed, 90 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
>

Reported warning comes from existing DTSI, I think, so:

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v3 0/2] arm64: dts: socfpga: agilex5: add NAND daughter board

[Dinh Nguyen]

On 2/10/25 01:46, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> 
> Agilex5 SoCFPGA devkit supports a separate NAND daughter board.
> Document NAND daughter board compatible string and add board file.
> 
> Changes in v3:
>    * Document Agilex5 NAND daughter board and use that compatible
>      in the device tree.
> 
> link to v2:
>   - https://lore.kernel.org/all/20250205101318.1778757-1-niravkumar.l.rabara@intel.com/
> 
> Changes in v2:
>   * Use nand flash node name according to dt bindings to fix dt build warnings.
>   * Arrange node in sequence.
> 
> link to v1:
>   - https://lore.kernel.org/all/20250107084831.2750035-1-niravkumar.l.rabara@intel.com/
> 
> Niravkumar L Rabara (2):
>    dt-bindings: intel: document Agilex5 NAND daughter board
>    arm64: dts: socfpga: agilex5: add NAND daughter board
> 
>   .../bindings/arm/intel,socfpga.yaml           |  1 +
>   arch/arm64/boot/dts/intel/Makefile            |  1 +
>   .../dts/intel/socfpga_agilex5_socdk_nand.dts  | 89 +++++++++++++++++++
>   3 files changed, 91 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_nand.dts
> 

Applied!

Thanks,
Dinh