From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Lux Aliaga <they@mint.lgbt>, Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 2/4] arm64: dts: qcom: sm6125: Add UFS nodes
Date: Thu, 15 Dec 2022 19:34:59 +0100 [thread overview]
Message-ID: <d387f52b-5c3e-9e3f-c5b9-4201a622abaf@linaro.org> (raw)
In-Reply-To: <8dcbd512-7f3b-919f-34ec-82e28b6282d3@mint.lgbt>
On 15.12.2022 19:33, Lux Aliaga wrote:
>
> On 15/12/2022 15:28, Konrad Dybcio wrote:
>> On 15.12.2022 19:24, Lux Aliaga wrote:
>>> Adds a UFS host controller node and its corresponding PHY to
>>> the sm6125 platform.
>>>
>>> Signed-off-by: Lux Aliaga <they@mint.lgbt>
>>> ---
>>> arch/arm64/boot/dts/qcom/sm6125.dtsi | 67 ++++++++++++++++++++++++++++
>>> 1 file changed, 67 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>> index 7e25a4f85594..22c945d5fc7a 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
>>> @@ -508,6 +508,73 @@ sdhc_2: mmc@4784000 {
>>> status = "disabled";
>>> };
>>> + ufs_mem_hc: ufs@4804000 {
>>> + compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
>>> + reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
>>> + reg-names = "std", "ice";
>>> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
>>> + phys = <&ufs_mem_phy_lanes>;
>>> + phy-names = "ufsphy";
>>> + lanes-per-direction = <1>;
>>> + #reset-cells = <1>;
>>> + resets = <&gcc GCC_UFS_PHY_BCR>;
>>> + reset-names = "rst";
>>> +
>>> + clock-names = "core_clk",
>>> + "bus_aggr_clk",
>>> + "iface_clk",
>>> + "core_clk_unipro",
>>> + "ref_clk",
>>> + "tx_lane0_sync_clk",
>>> + "rx_lane0_sync_clk",
>>> + "ice_core_clk";
>>> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>>> + <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
>>> + <&gcc GCC_UFS_PHY_AHB_CLK>,
>>> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>>> + <&rpmcc RPM_SMD_XO_CLK_SRC>,
>>> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>>> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
>>> + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
>>> + freq-table-hz = <50000000 240000000>,
>>> + <0 0>,
>>> + <0 0>,
>>> + <37500000 150000000>,
>>> + <0 0>,
>>> + <0 0>,
>>> + <0 0>,
>>> + <75000000 300000000>;
>>> +
>>> + non-removable;
>>> + status = "disabled";
>>> + };
>>> +
>>> + ufs_mem_phy: phy@4807000 {
>>> + compatible = "qcom,sm6115-qmp-ufs-phy";
>>> + reg = <0x04807000 0x1c4>;
>>> +
>>> + power-domains = <&gcc UFS_PHY_GDSC>;
>>> +
>>> + clock-names = "ref", "ref_aux";
>>> + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
>>> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
>>> +
>>> + resets = <&ufs_mem_hc 0>;
>>> + reset-names = "ufsphy";
>>> + status = "disabled";
>>> +
>>> + ufs_mem_phy_lanes: lanes@4807400 {
>>> + reg = <0x4807400 0x098>,
>>> + <0x4807600 0x130>,
>>> + <0x4807c00 0x16c>;
>>> + #phy-cells = <0>;
>>> + };
>>> +
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + ranges;
>> That won't compile. Properties must precede subnodes.
>>
>> Konrad
> Wait, so should I move it above the status property?
Status should be the last *property*.
If I'm not mistaken, this will not even compile as-is..
Konrad
>
next prev parent reply other threads:[~2022-12-15 18:37 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-15 18:24 [PATCH v3 1/4] dt-bindings: ufs: qcom: Add SM6125 compatible string Lux Aliaga
2022-12-15 18:24 ` [PATCH v3 2/4] arm64: dts: qcom: sm6125: Add UFS nodes Lux Aliaga
2022-12-15 18:28 ` Konrad Dybcio
2022-12-15 18:33 ` Lux Aliaga
2022-12-15 18:34 ` Konrad Dybcio [this message]
2022-12-15 18:24 ` [PATCH v3 3/4] dt-bindings: arm: qcom: Document xiaomi,laurel-sprout board Lux Aliaga
2022-12-15 18:24 ` [PATCH v3 4/4] arm64: dts: qcom: sm6125: Initial support for xiaomi-laurel-sprout Lux Aliaga
2022-12-15 18:34 ` Konrad Dybcio
2022-12-15 18:40 ` Lux Aliaga
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