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Thu, 10 Nov 2022 03:06:48 -0800 (PST) Received: from [192.168.31.208] ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id r9-20020a17090609c900b007aacfce2a91sm7067279eje.27.2022.11.10.03.06.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Nov 2022 03:06:47 -0800 (PST) Message-ID: Date: Thu, 10 Nov 2022 12:06:45 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Subject: Re: [PATCH 4/9] arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD To: Johan Hovold , Bjorn Andersson Cc: Andy Gross , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221110103558.12690-1-johan+linaro@kernel.org> <20221110103558.12690-5-johan+linaro@kernel.org> From: Konrad Dybcio In-Reply-To: <20221110103558.12690-5-johan+linaro@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 10/11/2022 11:35, Johan Hovold wrote: > Enable the NVMe SSD connected to PCIe2. > > Signed-off-by: Johan Hovold > --- > arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 63 +++++++++++++++++++++++ > 1 file changed, 63 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts > index 0801bd8c44fb..fd2bdfd1126b 100644 > --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts > @@ -50,6 +50,20 @@ vreg_edp_bl: regulator-edp-bl { > regulator-boot-on; > }; > > + vreg_nvme: regulator-nvme { > + compatible = "regulator-fixed"; > + > + regulator-name = "VCC3_SSD"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + > + gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&nvme_reg_en>; > + }; > + > vreg_misc_3p3: regulator-misc-3p3 { > compatible = "regulator-fixed"; > > @@ -178,6 +192,25 @@ vreg_l9d: ldo9 { > }; > }; > > +&pcie2a { > + perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; > + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; > + > + vddpe-3v3-supply = <&vreg_nvme>; > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie2a_default>; > + > + status = "okay"; > +}; > + > +&pcie2a_phy { > + vdda-phy-supply = <&vreg_l6d>; > + vdda-pll-supply = <&vreg_l4d>; > + > + status = "okay"; > +}; > + > &pmc8280c_lpg { > status = "okay"; > }; > @@ -393,6 +426,36 @@ reset-pins { > }; > }; > > + nvme_reg_en: nvme-reg-en-state { > + pins = "gpio135"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + pcie2a_default: pcie2a-default-state { Aren't they going to be identical for all boards anyway? Maybe there could be some commonization.. Konrad > + clkreq-n-pins { > + pins = "gpio142"; > + function = "pcie2a_clkreq"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + perst-n-pins { > + pins = "gpio143"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + wake-n-pins { > + pins = "gpio145"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + > qup0_i2c4_default: qup0-i2c4-default-state { > pins = "gpio171", "gpio172"; > function = "qup4";