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[2003:f6:ef1c:c500:ee59:d953:f148:40ba]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-378956654f4sm5443169f8f.43.2024.09.09.01.56.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Sep 2024 01:56:46 -0700 (PDT) Message-ID: Subject: Re: [PATCH v2 8/9] iio: dac: ad3552r: add axi platform driver From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Angelo Dureghello , Lars-Peter Clausen , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan Cc: linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Date: Mon, 09 Sep 2024 11:00:55 +0200 In-Reply-To: References: <20240905-wip-bl-ad3552r-axi-v0-iio-testing-v2-0-87d669674c00@baylibre.com> <20240905-wip-bl-ad3552r-axi-v0-iio-testing-v2-8-87d669674c00@baylibre.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi all, Some comments on top of what David already said... On Thu, 2024-09-05 at 15:40 -0500, David Lechner wrote: > On 9/5/24 10:17 AM, Angelo Dureghello wrote: >=20 > ... >=20 > > + > > +static int ad3552r_axi_read_raw(struct iio_dev *indio_dev, > > + struct iio_chan_spec const *chan, > > + int *val, int *val2, long mask) > > +{ > > + struct ad3552r_axi_state *st =3D iio_priv(indio_dev); > > + int err, ch =3D chan->channel; > > + > > + switch (mask) { > > + case IIO_CHAN_INFO_SAMP_FREQ: { > > + int clk_rate; > > + > > + err =3D iio_backend_read_raw(st->back, chan, &clk_rate, 0, > > + =C2=A0=C2=A0 IIO_CHAN_INFO_FREQUENCY); >=20 > This seems odd to me. How does the backend know what frequency we want? > It would make more sense to me if this somehow indicated that we were > getting the SPI SCLK rate. >=20 Yes, this sampling frequency bit seems very wrong atm. And the thing is, we= 're not even getting SCLK. According to [1], the /4 and /8 is for clk_in which = is not the same as SCLK (unless I'm missing something).=C2=A0 OTOH, if in the backend patch, that clk_get() is somehow getting sclk, that= 's wrong because sclk is an output clk of the IP. So we need to get clk_in whi= ch should be (typically) 133MHz. > > + if (err !=3D IIO_VAL_INT) >=20 > Would be better to call the variable ret instead of err if it can hold > something besides an error code. >=20 > > + return err; > > + > > + /* > > + * Data stream SDR/DDR (clk_in/8 or clk_in/4 update rate). > > + * Samplerate has sense in DDR only. >=20 > We should also mention that this assumes QSPI in addtion to DDR enabled. >=20 I understand the QSPI bit but why the DDR part? I just don't understand the comment "Samplerate has sense in DDR only.". It needs way more explanation = if that is true... > > + */ > > + if (st->single_channel) > > + clk_rate =3D DIV_ROUND_CLOSEST(clk_rate, 4); > > + else > > + clk_rate =3D DIV_ROUND_CLOSEST(clk_rate, 8); > > + >=20 This division also looks to be very backend dependent. So it's far from ide= al being in here... To me, the way we need to get this done is for the backend to effectively r= eport back SCLK (in a correct way). Then, depending on the number of bits per clk= (4 for QSPI), the word size and DDR vs SDR we get the device sample rate. With= it, we then choose one of Jonathan's suggestion (a per channel attr might be le= ss confusing). All the above said, I probably need to catch up on the above. It might happ= en that David and Angelo already got some more info from the hdl guys while I = was on vacation. [1]: https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html - Nuno S=C3=A1