Re: [PATCH 03/10] dt-bindings: display: imx: Add i.MX8qxp Display Controller pixel engine

[Krzysztof Kozlowski <krzk@kernel.org>]

On 08/07/2024 08:47, Liu Ying wrote:
> On 07/07/2024, Krzysztof Kozlowski wrote:
>> On 05/07/2024 11:09, Liu Ying wrote:
>>> i.MX8qxp Display Controller pixel engine consists of all processing units
>>> that operate in the AXI bus clock domain.  Command sequencer and interrupt
>>> controller of the Display Controller work with AXI bus clock, but they are
>>> not in pixel engine.
>>>
>>> Signed-off-by: Liu Ying <victor.liu@nxp.com>
>>> ---
>>
>>
>>> +
>>> +        extdst@56180a40 {
>>> +            compatible = "fsl,imx8qxp-dc-extdst";
>>> +            reg = <0x56180a40 0x7>, <0x56186000 0x400>;
>>> +            reg-names = "pec", "cfg";
>>> +            interrupt-parent = <&dc0_intc>;
>>> +            interrupts = <12>, <13>, <14>;
>>> +            interrupt-names = "shdload", "framecomplete", "seqcomplete";
>>> +            fsl,dc-ed-id = <5>;
>>> +        };
>>> +
>>> +        fetchwarp@56180a60 {
>>> +            compatible = "fsl,imx8qxp-dc-fetchwarp";
>>> +            reg = <0x56180a60 0x4>, <0x56186400 0x400>;
>>
>> Aha, one word for address range.
> 
> Sorry, I don't get your idea here.

How many words are in the first IO address range?

One.

That is not a separate device.

> 
>>
>> Sorry, these are not separate devices.
> 
> Hmm, again, Maxime suggested to use separate devices.

To some level you can create separate devices, but for one register?

Best regards,
Krzysztof