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Wed, 16 Jul 2025 02:28:49 -0700 (PDT) Message-ID: Date: Wed, 16 Jul 2025 11:28:48 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] media: iris: Add support for SM8750 (VPU v3.5) To: Dikshita Agarwal , Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250714-sm8750-iris-v1-0-3006293a5bc7@linaro.org> <20250714-sm8750-iris-v1-3-3006293a5bc7@linaro.org> <7b0a984f-b62a-ac4d-74bf-a6e839c59272@quicinc.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzysztof.kozlowski@linaro.org; keydata= xsFNBFVDQq4BEAC6KeLOfFsAvFMBsrCrJ2bCalhPv5+KQF2PS2+iwZI8BpRZoV+Bd5kWvN79 cFgcqTTuNHjAvxtUG8pQgGTHAObYs6xeYJtjUH0ZX6ndJ33FJYf5V3yXqqjcZ30FgHzJCFUu JMp7PSyMPzpUXfU12yfcRYVEMQrmplNZssmYhiTeVicuOOypWugZKVLGNm0IweVCaZ/DJDIH gNbpvVwjcKYrx85m9cBVEBUGaQP6AT7qlVCkrf50v8bofSIyVa2xmubbAwwFA1oxoOusjPIE J3iadrwpFvsZjF5uHAKS+7wHLoW9hVzOnLbX6ajk5Hf8Pb1m+VH/E8bPBNNYKkfTtypTDUCj NYcd27tjnXfG+SDs/EXNUAIRefCyvaRG7oRYF3Ec+2RgQDRnmmjCjoQNbFrJvJkFHlPeHaeS BosGY+XWKydnmsfY7SSnjAzLUGAFhLd/XDVpb1Een2XucPpKvt9ORF+48gy12FA5GduRLhQU vK4tU7ojoem/G23PcowM1CwPurC8sAVsQb9KmwTGh7rVz3ks3w/zfGBy3+WmLg++C2Wct6nM Pd8/6CBVjEWqD06/RjI2AnjIq5fSEH/BIfXXfC68nMp9BZoy3So4ZsbOlBmtAPvMYX6U8VwD TNeBxJu5Ex0Izf1NV9CzC3nNaFUYOY8KfN01X5SExAoVTr09ewARAQABzTRLcnp5c3p0b2Yg S296bG93c2tpIDxrcnp5c3p0b2Yua296bG93c2tpQGxpbmFyby5vcmc+wsGUBBMBCgA+FiEE m9B+DgxR+NWWd7dUG5NDfTtBYpsFAmI+BxMCGwMFCRRfreEFCwkIBwIGFQoJCAsCBBYCAwEC HgECF4AACgkQG5NDfTtBYptgbhAAjAGunRoOTduBeC7V6GGOQMYIT5n3OuDSzG1oZyM4kyvO XeodvvYv49/ng473E8ZFhXfrre+c1olbr1A8pnz9vKVQs9JGVa6wwr/6ddH7/yvcaCQnHRPK mnXyP2BViBlyDWQ71UC3N12YCoHE2cVmfrn4JeyK/gHCvcW3hUW4i5rMd5M5WZAeiJj3rvYh v8WMKDJOtZFXxwaYGbvFJNDdvdTHc2x2fGaWwmXMJn2xs1ZyFAeHQvrp49mS6PBQZzcx0XL5 cU9ZjhzOZDn6Apv45/C/lUJvPc3lo/pr5cmlOvPq1AsP6/xRXsEFX/SdvdxJ8w9KtGaxdJuf rpzLQ8Ht+H0lY2On1duYhmro8WglOypHy+TusYrDEry2qDNlc/bApQKtd9uqyDZ+rx8bGxyY qBP6bvsQx5YACI4p8R0J43tSqWwJTP/R5oPRQW2O1Ye1DEcdeyzZfifrQz58aoZrVQq+innR aDwu8qDB5UgmMQ7cjDSeAQABdghq7pqrA4P8lkA7qTG+aw8Z21OoAyZdUNm8NWJoQy8m4nUP gmeeQPRc0vjp5JkYPgTqwf08cluqO6vQuYL2YmwVBIbO7cE7LNGkPDA3RYMu+zPY9UUi/ln5 dcKuEStFZ5eqVyqVoZ9eu3RTCGIXAHe1NcfcMT9HT0DPp3+ieTxFx6RjY3kYTGLOwU0EVUNc NAEQAM2StBhJERQvgPcbCzjokShn0cRA4q2SvCOvOXD+0KapXMRFE+/PZeDyfv4dEKuCqeh0 hihSHlaxTzg3TcqUu54w2xYskG8Fq5tg3gm4kh1Gvh1LijIXX99ABA8eHxOGmLPRIBkXHqJY oHtCvPc6sYKNM9xbp6I4yF56xVLmHGJ61KaWKf5KKWYgA9kfHufbja7qR0c6H79LIsiYqf92 H1HNq1WlQpu/fh4/XAAaV1axHFt/dY/2kU05tLMj8GjeQDz1fHas7augL4argt4e+jum3Nwt yupodQBxncKAUbzwKcDrPqUFmfRbJ7ARw8491xQHZDsP82JRj4cOJX32sBg8nO2N5OsFJOcd 5IE9v6qfllkZDAh1Rb1h6DFYq9dcdPAHl4zOj9EHq99/CpyccOh7SrtWDNFFknCmLpowhct9 5ZnlavBrDbOV0W47gO33WkXMFI4il4y1+Bv89979rVYn8aBohEgET41SpyQz7fMkcaZU+ok/ +HYjC/qfDxT7tjKXqBQEscVODaFicsUkjheOD4BfWEcVUqa+XdUEciwG/SgNyxBZepj41oVq FPSVE+Ni2tNrW/e16b8mgXNngHSnbsr6pAIXZH3qFW+4TKPMGZ2rZ6zITrMip+12jgw4mGjy 5y06JZvA02rZT2k9aa7i9dUUFggaanI09jNGbRA/ABEBAAHCwXwEGAEKACYCGwwWIQSb0H4O DFH41ZZ3t1Qbk0N9O0FimwUCaBdQXwUJFpZbKgAKCRAbk0N9O0Fim07TD/92Vcmzn/jaEBcq yT48ODfDIQVvg2nIDW+qbHtJ8DOT0d/qVbBTU7oBuo0xuHo+MTBp0pSTWbThLsSN1AuyP8wF KChC0JPcwOZZRS0dl3lFgg+c+rdZUHjsa247r+7fvm2zGG1/u+33lBJgnAIH5lSCjhP4VXiG q5ngCxGRuBq+0jNCKyAOC/vq2cS/dgdXwmf2aL8G7QVREX7mSl0x+CjWyrpFc1D/9NV/zIWB G1NR1fFb+oeOVhRGubYfiS62htUQjGLK7qbTmrd715kH9Noww1U5HH7WQzePt/SvC0RhQXNj XKBB+lwwM+XulFigmMF1KybRm7MNoLBrGDa3yGpAkHMkJ7NM4iSMdSxYAr60RtThnhKc2kLI zd8GqyBh0nGPIL+1ZVMBDXw1Eu0/Du0rWt1zAKXQYVAfBLCTmkOnPU0fjR7qVT41xdJ6KqQM NGQeV+0o9X91X6VBeK6Na3zt5y4eWkve65DRlk1aoeBmhAteioLZlXkqu0pZv+PKIVf+zFKu h0At/TN/618e/QVlZPbMeNSp3S3ieMP9Q6y4gw5CfgiDRJ2K9g99m6Rvlx1qwom6QbU06ltb vJE2K9oKd9nPp1NrBfBdEhX8oOwdCLJXEq83vdtOEqE42RxfYta4P3by0BHpcwzYbmi/Et7T 2+47PN9NZAOyb771QoVr8A== In-Reply-To: <7b0a984f-b62a-ac4d-74bf-a6e839c59272@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 16/07/2025 11:10, Dikshita Agarwal wrote: > > > On 7/14/2025 7:11 PM, Krzysztof Kozlowski wrote: >> Add support for SM8750 Iris codec with major differences against >> previous generation SM8650: >> >> 1. New clocks and new resets, thus new power up and power down >> sequences, >> >> 2. New WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 register programmed >> during boot-up >> Please kindly trim the replies from unnecessary context. It makes it much easier to find new content. >> +struct iris_platform_data sm8750_data = { >> + .get_instance = iris_hfi_gen2_get_instance, >> + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, >> + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, >> + .vpu_ops = &iris_vpu35_ops, >> + .set_preset_registers = iris_set_sm8550_preset_registers, >> + .icc_tbl = sm8550_icc_table, >> + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), >> + .clk_rst_tbl = sm8750_clk_reset_table, >> + .clk_rst_tbl_size = ARRAY_SIZE(sm8750_clk_reset_table), >> + .bw_tbl_dec = sm8550_bw_table_dec, >> + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), >> + .pmdomain_tbl = sm8550_pmdomain_table, >> + .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), >> + .opp_pd_tbl = sm8550_opp_pd_table, >> + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), >> + .clk_tbl = sm8750_clk_table, >> + .clk_tbl_size = ARRAY_SIZE(sm8750_clk_table), >> + /* Upper bound of DMA address range */ >> + .dma_mask = 0xe0000000 - 1, >> + .fwname = "qcom/vpu/vpu35_4v.mbn", > Could you clarify where this firmware has been merged? Also, it appears > that the naming convention hasn't been followed. I mentioned in the DTS patchset but not here, so I will add it in the cover letter - firmware is not released. About the name I cannot comment, that's the name I got from qcom. Happy to use whatever name you prefer. >> +static int iris_vpu35_power_on_hw(struct iris_core *core) >> +{ >> + int ret; >> + u32 val; >> + >> + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); >> + if (ret) >> + return ret; >> + >> + /* Switch GDSC to SW control */ >> + writel(0x0, core->reg_base + WRAPPER_CORE_POWER_CONTROL); > GDSCs have been transitioned from HW_CTRL to HW_CTRL_TRIGGER, placing them > under software control by default, what is the need of doing this? >> + ret = readl_poll_timeout(core->reg_base + WRAPPER_CORE_POWER_STATUS, >> + val, val & BIT(1), 200, 2000); The need comes from differences between this and previous generation, mostly based on downstream sources. I think the hardware just did not boot up without it. You need to fix your email client to add line breaks around your replies, because it is very difficult to spot them. It's close to impossible... >> + if (ret) >> + goto err_disable_power; >> + >> + ret = iris_prepare_enable_clock(core, IRIS_AXI_CLK); >> + if (ret) >> + goto err_gdsc; >> + >> + ret = iris_prepare_enable_clock(core, IRIS_HW_FREERUN_CLK); >> + if (ret) >> + goto err_disable_axi_clk; >> + >> + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); >> + if (ret) >> + goto err_disable_hw_free_clk; >> + >> + ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true); >> + if (ret) >> + goto err_disable_hw_clk; >> + >> + return 0; >> + >> +err_disable_hw_clk: >> + iris_disable_unprepare_clock(core, IRIS_HW_CLK); >> +err_disable_hw_free_clk: >> + iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK); >> +err_disable_axi_clk: >> + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); >> +err_gdsc: >> + writel(BIT(0), core->reg_base + WRAPPER_CORE_POWER_CONTROL); >> +err_disable_power: >> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); >> + >> + return ret; >> +} >> + >> +static void iris_vpu35_power_off_hw(struct iris_core *core) >> +{ >> + u32 val = 0, value, i; >> + int ret; >> + >> + if (iris_vpu3x_hw_power_collapsed(core)) >> + goto disable_power; >> + >> + value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); >> + if (value) >> + writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); >> + >> + for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) { >> + ret = readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 * i, >> + val, val & 0x400000, 2000, 20000); >> + if (ret) >> + goto disable_power; >> + } >> + >> + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, >> + val, val & BIT(0), 200, 2000); > what are you polling here for? This is not different than existing code. I don't understand why you are commenting on something which is already there. >> + if (ret) >> + goto disable_power; >> + >> + /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */ > Could you share the reference for this sqeunece, this looks half-cooked. > Would recommend following Hardware programmin guide(HPG) for this. Why? Look at existing code. It's the same. I think I responded to all your comments - it barely possible to spot them in the quote. Best regards, Krzysztof