From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CD2A22068F; Mon, 24 Nov 2025 11:02:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763982121; cv=none; b=sr+alq76p3mAvcR7rnkTcrXoG6qFi9UyYyMDbJ4V4ZU8Q9poVEbGldxZfY4KVQOhkdw5Pkx/fLuvTAL96EO6IN7HKkTAHxDhSclDJaUxRCDiRiyMo725/5WlYxtHpAtIU/UKd9xkyzwhoth6uVa2UlgR/7p1l5KETzSuuvqMbg0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763982121; c=relaxed/simple; bh=5yQwGr1/pbPjCyfg6TPiWd9jFRt4jfCH8hsUv6oL3yE=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=QwWPfU/I8ldvDEcVvuOLhWraH3SDn/SH3TokFim5/2cv9Xas5lk9PpNq0t9SxmkQNkJED8MjnQVm0yMxWfv7UqmShwtOTWY16X2koPO3XLjBczeHpQu9cJ8nvHRwuo+TUSCLBcMVl+K2Dttc4p9AY9sJUbsLPwN5zMw6wd8DJfw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ClvydOwc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ClvydOwc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3BC77C4CEF1; Mon, 24 Nov 2025 11:01:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763982120; bh=5yQwGr1/pbPjCyfg6TPiWd9jFRt4jfCH8hsUv6oL3yE=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=ClvydOwcxIZ/QmFPbloxmstWi9B5ijiLtxK7AN9a1kls7Ki4WZr+rhTC1doL+c1U2 W/OSWae2uHBHL7pnrKGfSSSvx7ZbdTsDnyI6bwbH7tlNzoB+5gWMdjxj7qtXRCfY3I n3dbPTKMiOBKHmOw0KdecqSVrlnztU9gwGmiNTRaYAEIhIjlC9CEqzMAmOs4jLRlW2 OwpDbc8nwyYvgEAfIDHbeE4n3jyxmETfGKaAqbdRaBAx1dvvrahw/gqOVF1/xlvUJS GKqwl5AbRcZNX2S6vuby5RcNTj8wrWiCEzmmYWufZUrI1mw+pr/o//kjsFGHP85TWI uoY3NJRPbkVPw== Message-ID: Date: Mon, 24 Nov 2025 12:01:53 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/9] dt-bindings: display: add verisilicon,dc To: Icenowy Zheng , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski Cc: Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng References: <20251124105226.2860845-1-uwu@icenowy.me> <20251124105226.2860845-3-uwu@icenowy.me> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 24/11/2025 11:52, Icenowy Zheng wrote: > Verisilicon has a series of display controllers prefixed with DC and > with self-identification facility like their GC series GPUs. > > Add a device tree binding for it. > > Depends on the specific DC model, it can have either one or two display > outputs, and each display output could be set to DPI signal or "DP" > signal (which seems to be some plain parallel bus to HDMI controllers). > > Signed-off-by: Icenowy Zheng > Signed-off-by: Icenowy Zheng Wrong DCO chain order. You send it as icenowy.me, so this must be last SoB. This identity is the last one certifying DCO. Please kindly read submitting patches, so you know what you are certifying here. > --- > Changes in v3: > - Added SoC-specific compatible string, and arm the binding with clock / > port checking for the specific SoC (with a 2-output DC). > > Changes in v2: > - Fixed misspelt "versilicon" in title. > - Moved minItems in clock properties to be earlier than items. > - Re-aligned multi-line clocks and resets in example. > > .../bindings/display/verisilicon,dc.yaml | 146 ++++++++++++++++++ > 1 file changed, 146 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > new file mode 100644 > index 0000000000000..522a544498bea > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > @@ -0,0 +1,146 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Verisilicon DC-series display controllers > + > +maintainers: > + - Icenowy Zheng > + > +properties: > + $nodename: > + pattern: "^display@[0-9a-f]+$" > + > + compatible: > + items: > + - enum: > + - thead,th1520-dc8200 > + - const: verisilicon,dc I do not see any explanation of exception for generic compatibles, maybe except "self-identification" remark. Rob already pointed this out, so be explicit in commit msg why you are using a generic compatible. > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + minItems: 4 This is not flexible. Device either has or has not these clocks. > + items: > + - description: DC Core clock > + - description: DMA AXI bus clock > + - description: Configuration AHB bus clock > + - description: Pixel clock of output 0 > + - description: Pixel clock of output 1 > + Best regards, Krzysztof