[PATCH 0/5] Add RSPIs support for RZ/G3E SoC

[PATCH 0/5] Add RSPIs support for RZ/G3E SoC

[Tommaso Merciai]

Dear All,

This patch series adds RSPIs support for the Renesas
RZ/G3E (a.k.a R9A09G047) R9A09G047 SoC.

Series apply on top of [0].

[0] https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com/

Kind Regards,
Tommaso

Tommaso Merciai (5):
  clk: renesas: r9a09g047: Add entries for the RSPIs
  spi: dt-bindings: renesas,rzv2h-rspi: Document dmas property
  spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support
  arm64: dts: renesas: r9a09g047: Add RSPI nodes
  arm64: dts: renesas: r9a09g047e57-smarc: Enable RSPI0

 .../bindings/spi/renesas,rzv2h-rspi.yaml      |  7 +-
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    | 84 +++++++++++++++++++
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   | 16 ++++
 drivers/clk/renesas/r9a09g047-cpg.c           | 24 ++++++
 4 files changed, 130 insertions(+), 1 deletion(-)

-- 
2.43.0

[PATCH 1/5] clk: renesas: r9a09g047: Add entries for the RSPIs

[Tommaso Merciai]

Add clock and reset entries for the Renesas RZ/G3E RSPI IPs.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 drivers/clk/renesas/r9a09g047-cpg.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 1e9896742a06..45e2d9f93b92 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -224,6 +224,24 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
 						BUS_MSTOP(5, BIT(13))),
 	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,
 						BUS_MSTOP(5, BIT(13))),
+	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,
+						BUS_MSTOP(11, BIT(0))),
+	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,
+						BUS_MSTOP(11, BIT(0))),
+	DEF_MOD("rspi_0_tclk",			CLK_PLLCLN_DIV8, 5, 6, 2, 22,
+						BUS_MSTOP(11, BIT(0))),
+	DEF_MOD("rspi_1_pclk",			CLK_PLLCLN_DIV8, 5, 7, 2, 23,
+						BUS_MSTOP(11, BIT(1))),
+	DEF_MOD("rspi_1_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 8, 2, 24,
+						BUS_MSTOP(11, BIT(1))),
+	DEF_MOD("rspi_1_tclk",			CLK_PLLCLN_DIV8, 5, 9, 2, 25,
+						BUS_MSTOP(11, BIT(1))),
+	DEF_MOD("rspi_2_pclk",			CLK_PLLCLN_DIV8, 5, 10, 2, 26,
+						BUS_MSTOP(11, BIT(2))),
+	DEF_MOD("rspi_2_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 11, 2, 27,
+						BUS_MSTOP(11, BIT(2))),
+	DEF_MOD("rspi_2_tclk",			CLK_PLLCLN_DIV8, 5, 12, 2, 28,
+						BUS_MSTOP(11, BIT(2))),
 	DEF_MOD("rsci0_pclk",			CLK_PLLCLN_DIV16, 5, 13, 2, 29,
 						BUS_MSTOP(11, BIT(3))),
 	DEF_MOD("rsci0_tclk",			CLK_PLLCLN_DIV16, 5, 14, 2, 30,
@@ -457,6 +475,12 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
 	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
 	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */
 	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
+	DEF_RST(7, 11, 3, 12),		/* RSPI_0_PRESETN */
+	DEF_RST(7, 12, 3, 13),		/* RSPI_0_TRESETN */
+	DEF_RST(7, 13, 3, 14),		/* RSPI_1_PRESETN */
+	DEF_RST(7, 14, 3, 15),		/* RSPI_1_TRESETN */
+	DEF_RST(7, 15, 3, 16),		/* RSPI_2_PRESETN */
+	DEF_RST(8, 0, 3, 17),		/* RSPI_2_TRESETN */
 	DEF_RST(8, 1, 3, 18),		/* RSCI0_PRESETN */
 	DEF_RST(8, 2, 3, 19),		/* RSCI0_TRESETN */
 	DEF_RST(8, 3, 3, 20),		/* RSCI1_PRESETN */
-- 
2.43.0

Re: [PATCH 1/5] clk: renesas: r9a09g047: Add entries for the RSPIs

[Geert Uytterhoeven]

On Tue, 17 Feb 2026 at 17:24, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> Add clock and reset entries for the Renesas RZ/G3E RSPI IPs.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v7.1.

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 2/5] spi: dt-bindings: renesas,rzv2h-rspi: Document dmas property

[Tommaso Merciai]

Document the dmas property to state it must be specified as TX/RX DMA
specifier pairs.
This clarifies the expected ordering and improves binding readability
without changing behavior.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 - This patch depend up on [0]
 - [0] https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com/

 Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
index cf8b733b766d..d6a5338d6521 100644
--- a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
+++ b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
@@ -60,6 +60,9 @@ properties:
   dmas:
     minItems: 2
     maxItems: 10
+    description:
+      Must contain a list of pairs of references to DMA specifiers, one for
+      transmission, and one for reception.
 
   dma-names:
     minItems: 2
-- 
2.43.0

Re: [PATCH 2/5] spi: dt-bindings: renesas,rzv2h-rspi: Document dmas property

[Mark Brown]

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On Tue, Feb 17, 2026 at 05:23:46PM +0100, Tommaso Merciai wrote:

>  - This patch depend up on [0]
>  - [0] https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com/

Please include human readable descriptions of things like commits and
issues being discussed in e-mail in your mails, this makes them much
easier for humans to read especially when they have no internet access.
I do frequently catch up on my mail on flights or while otherwise
travelling so this is even more pressing for me than just being about
making things a bit easier to read.

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Re: [PATCH 2/5] spi: dt-bindings: renesas,rzv2h-rspi: Document dmas property

[Krzysztof Kozlowski]

On Tue, Feb 17, 2026 at 05:23:46PM +0100, Tommaso Merciai wrote:
> Document the dmas property to state it must be specified as TX/RX DMA
> specifier pairs.
> This clarifies the expected ordering and improves binding readability
> without changing behavior.
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
>  - This patch depend up on [0]
>  - [0] https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com/

So just squash it there....

Why are you adding comment to correct code which is in-flight, not
applied? Just REVIEW the other!

Best regards,
Krzysztof

Re: [PATCH 2/5] spi: dt-bindings: renesas,rzv2h-rspi: Document dmas property

[Geert Uytterhoeven]

On Tue, 17 Feb 2026 at 17:24, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> Document the dmas property to state it must be specified as TX/RX DMA
> specifier pairs.
> This clarifies the expected ordering and improves binding readability
> without changing behavior.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
>  - This patch depend up on [0]
>  - [0] https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com/

The dependency is now in spi/for-next.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support

[Tommaso Merciai]

Document the RSPI controller on the Renesas RZ/G3E SoC. The block is
compatible with the RSPI implementation found on the RZ/V2H(P) family.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 - This patch depend up on [0]
 - [0] https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com/

 Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
index d6a5338d6521..2c9045fd51de 100644
--- a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
+++ b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
@@ -16,7 +16,9 @@ properties:
           - renesas,r9a09g057-rspi # RZ/V2H(P)
           - renesas,r9a09g077-rspi # RZ/T2H
       - items:
-          - const: renesas,r9a09g056-rspi # RZ/V2N
+          - enum:
+              - renesas,r9a09g047-rspi # RZ/G3E
+              - renesas,r9a09g056-rspi # RZ/V2N
           - const: renesas,r9a09g057-rspi
       - items:
           - const: renesas,r9a09g087-rspi # RZ/N2H
-- 
2.43.0

Re: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support

[Krzysztof Kozlowski]

On Tue, Feb 17, 2026 at 05:23:47PM +0100, Tommaso Merciai wrote:
> Document the RSPI controller on the Renesas RZ/G3E SoC. The block is
> compatible with the RSPI implementation found on the RZ/V2H(P) family.
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
>  - This patch depend up on [0]
>  - [0] https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com/

I am not even looking there, start reviewing each other patches, so you
won't be sending FIXES instead of reviews.

Best regards,
Krzysztof

Re: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support

[Krzysztof Kozlowski]

On 18/02/2026 08:50, Krzysztof Kozlowski wrote:
> On Tue, Feb 17, 2026 at 05:23:47PM +0100, Tommaso Merciai wrote:
>> Document the RSPI controller on the Renesas RZ/G3E SoC. The block is
>> compatible with the RSPI implementation found on the RZ/V2H(P) family.
>>
>> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
>> ---
>>  - This patch depend up on [0]
>>  - [0] https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com/
> 
> I am not even looking there, start reviewing each other patches, so you
> won't be sending FIXES instead of reviews.

You kind of ignored the problem and the other patch got merged.

Best regards,
Krzysztof

RE: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support

[Biju Das]

Hi Krzysztof Kozlowski,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 04 March 2026 15:06
> Subject: Re: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support
> 
> On 18/02/2026 08:50, Krzysztof Kozlowski wrote:
> > On Tue, Feb 17, 2026 at 05:23:47PM +0100, Tommaso Merciai wrote:
> >> Document the RSPI controller on the Renesas RZ/G3E SoC. The block is
> >> compatible with the RSPI implementation found on the RZ/V2H(P) family.
> >>
> >> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> >> ---
> >>  - This patch depend up on [0]
> >>  - [0]
> >> https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel.t
> >> anislav.xa@renesas.com/
> >
> > I am not even looking there, start reviewing each other patches, so
> > you won't be sending FIXES instead of reviews.
> 
> You kind of ignored the problem and the other patch got merged.

We prepared a patch updating the description and it is under internal review:

This will cover any combinations.

  description:
      Must contain unique references to DMA specifiers, with at least one
      for transmission and one for reception. Each category may include
      multiple entries, constrained only by the total number of DMACs
      available on the SoC.

Cheers,
Biju

Re: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support

[Krzysztof Kozlowski]

On 04/03/2026 16:34, Biju Das wrote:
> Hi Krzysztof Kozlowski,
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: 04 March 2026 15:06
>> Subject: Re: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support
>>
>> On 18/02/2026 08:50, Krzysztof Kozlowski wrote:
>>> On Tue, Feb 17, 2026 at 05:23:47PM +0100, Tommaso Merciai wrote:
>>>> Document the RSPI controller on the Renesas RZ/G3E SoC. The block is
>>>> compatible with the RSPI implementation found on the RZ/V2H(P) family.
>>>>
>>>> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
>>>> ---
>>>>  - This patch depend up on [0]
>>>>  - [0]
>>>> https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel.t
>>>> anislav.xa@renesas.com/
>>>
>>> I am not even looking there, start reviewing each other patches, so
>>> you won't be sending FIXES instead of reviews.
>>
>> You kind of ignored the problem and the other patch got merged.
> 
> We prepared a patch updating the description and it is under internal review:

That's not the point. The point was that you give PUBLIC review that
mentioned patch is incomplete and must be changed.

Not prepare a follow-up patch. That's exactly my complain I raised, so
you solved nothing.

> 
> This will cover any combinations.
> 
>   description:
>       Must contain unique references to DMA specifiers, with at least one
>       for transmission and one for reception. Each category may include
>       multiple entries, constrained only by the total number of DMACs
>       available on the SoC.

No. Solves nothing. Renesas folks were supposed to review patches
instead of letting poor code be merged to THEN develop fixes.


Best regards,
Krzysztof

RE: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support

[Biju Das]

Hi Krzysztof Kozlowski,

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: 04 March 2026 15:40
> Subject: Re: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support
> 
> On 04/03/2026 16:34, Biju Das wrote:
> > Hi Krzysztof Kozlowski,
> >
> >> -----Original Message-----
> >> From: Krzysztof Kozlowski <krzk@kernel.org>
> >> Sent: 04 March 2026 15:06
> >> Subject: Re: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi:
> >> Document RZ/G3E SoC support
> >>
> >> On 18/02/2026 08:50, Krzysztof Kozlowski wrote:
> >>> On Tue, Feb 17, 2026 at 05:23:47PM +0100, Tommaso Merciai wrote:
> >>>> Document the RSPI controller on the Renesas RZ/G3E SoC. The block
> >>>> is compatible with the RSPI implementation found on the RZ/V2H(P) family.
> >>>>
> >>>> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> >>>> ---
> >>>>  - This patch depend up on [0]
> >>>>  - [0]
> >>>> https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel
> >>>> .t
> >>>> anislav.xa@renesas.com/
> >>>
> >>> I am not even looking there, start reviewing each other patches, so
> >>> you won't be sending FIXES instead of reviews.
> >>
> >> You kind of ignored the problem and the other patch got merged.
> >
> > We prepared a patch updating the description and it is under internal review:
> 
> That's not the point. The point was that you give PUBLIC review that mentioned patch is incomplete and
> must be changed.
> 
> Not prepare a follow-up patch. That's exactly my complain I raised, so you solved nothing.

We were supposed to send a v2 with description after your review, by the time the other patch got merged.

Now we prepared an incremental patch just for updating the description and it is under internal review.

> 
> >
> > This will cover any combinations.
> >
> >   description:
> >       Must contain unique references to DMA specifiers, with at least one
> >       for transmission and one for reception. Each category may include
> >       multiple entries, constrained only by the total number of DMACs
> >       available on the SoC.
> 
> No. Solves nothing. Renesas folks were supposed to review patches instead of letting poor code be
> merged to THEN develop fixes.

Why you think this description won't fix the issue with multiple DMACS?

It will cover all the invalid cases for eg: Num DMACs = 5

{rx} --> Covered by DMA specifiers with at least one for transmission and one for reception.
{tx}
{rx, rx, rx, rx, rx, rx } --> Covered by the total number of DMACs available on the SoC.
{tx, tx, tx, tx, tx, tx }
....
....

Cheers,
Biju

Re: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support

[Krzysztof Kozlowski]

On 04/03/2026 16:52, Biju Das wrote:
> Hi Krzysztof Kozlowski,
> 
>> -----Original Message-----
>> From: Krzysztof Kozlowski <krzk@kernel.org>
>> Sent: 04 March 2026 15:40
>> Subject: Re: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support
>>
>> On 04/03/2026 16:34, Biju Das wrote:
>>> Hi Krzysztof Kozlowski,
>>>
>>>> -----Original Message-----
>>>> From: Krzysztof Kozlowski <krzk@kernel.org>
>>>> Sent: 04 March 2026 15:06
>>>> Subject: Re: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi:
>>>> Document RZ/G3E SoC support
>>>>
>>>> On 18/02/2026 08:50, Krzysztof Kozlowski wrote:
>>>>> On Tue, Feb 17, 2026 at 05:23:47PM +0100, Tommaso Merciai wrote:
>>>>>> Document the RSPI controller on the Renesas RZ/G3E SoC. The block
>>>>>> is compatible with the RSPI implementation found on the RZ/V2H(P) family.
>>>>>>
>>>>>> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
>>>>>> ---
>>>>>>  - This patch depend up on [0]
>>>>>>  - [0]
>>>>>> https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel
>>>>>> .t
>>>>>> anislav.xa@renesas.com/
>>>>>
>>>>> I am not even looking there, start reviewing each other patches, so
>>>>> you won't be sending FIXES instead of reviews.
>>>>
>>>> You kind of ignored the problem and the other patch got merged.
>>>
>>> We prepared a patch updating the description and it is under internal review:
>>
>> That's not the point. The point was that you give PUBLIC review that mentioned patch is incomplete and
>> must be changed.
>>
>> Not prepare a follow-up patch. That's exactly my complain I raised, so you solved nothing.
> 
> We were supposed to send a v2 with description after your review, by the time the other patch got merged.
> 
> Now we prepared an incremental patch just for updating the description and it is under internal review.
> 
>>
>>>
>>> This will cover any combinations.
>>>
>>>   description:
>>>       Must contain unique references to DMA specifiers, with at least one
>>>       for transmission and one for reception. Each category may include
>>>       multiple entries, constrained only by the total number of DMACs
>>>       available on the SoC.
>>
>> No. Solves nothing. Renesas folks were supposed to review patches instead of letting poor code be
>> merged to THEN develop fixes.
> 
> Why you think this description won't fix the issue with multiple DMACS?

Because I asked you TO REVIEW the patch while it was inflight.

Did it happen? No.

Explain me how posting patch now solves the past events, that patch was
already merged and no review from Renesas was given?


Best regards,
Krzysztof

Re: [PATCH 3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support

[Geert Uytterhoeven]

On Tue, 17 Feb 2026 at 17:25, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> Document the RSPI controller on the Renesas RZ/G3E SoC. The block is
> compatible with the RSPI implementation found on the RZ/V2H(P) family.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
>  - This patch depend up on [0]
>  - [0] https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com/

The dependency is now in spi/for-next.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 4/5] arm64: dts: renesas: r9a09g047: Add RSPI nodes

[Tommaso Merciai]

Add nodes for the RSPI IPs found in the Renesas RZ/G3E SoC.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 84 ++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index cbb48ff5028f..94d23cc013f7 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -591,6 +591,90 @@ channel5 {
 			};
 		};
 
+		rspi0: spi@12800000 {
+			compatible = "renesas,r9a09g047-rspi", "renesas,r9a09g057-rspi";
+			reg = <0x0 0x12800000 0x0 0x400>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "idle", "error", "end", "rx", "tx";
+			clocks = <&cpg CPG_MOD 0x54>,
+				 <&cpg CPG_MOD 0x55>,
+				 <&cpg CPG_MOD 0x56>;
+			clock-names = "pclk", "pclk_sfr", "tclk";
+			resets = <&cpg 0x7b>, <&cpg 0x7c>;
+			reset-names = "presetn", "tresetn";
+			dmas = <&dmac0 0x448c>, <&dmac0 0x448d>,
+			       <&dmac1 0x448c>, <&dmac1 0x448d>,
+			       <&dmac2 0x448c>, <&dmac2 0x448d>,
+			       <&dmac3 0x448c>, <&dmac3 0x448d>,
+			       <&dmac4 0x448c>, <&dmac4 0x448d>;
+			dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
+				    "rx", "tx", "rx", "tx";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		rspi1: spi@12800400 {
+			compatible = "renesas,r9a09g047-rspi", "renesas,r9a09g057-rspi";
+			reg = <0x0 0x12800400 0x0 0x400>;
+			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "idle", "error", "end", "rx", "tx";
+			clocks = <&cpg CPG_MOD 0x57>,
+				 <&cpg CPG_MOD 0x58>,
+				 <&cpg CPG_MOD 0x59>;
+			clock-names = "pclk", "pclk_sfr", "tclk";
+			resets = <&cpg 0x7d>, <&cpg 0x7e>;
+			reset-names = "presetn", "tresetn";
+			dmas = <&dmac0 0x448e>, <&dmac0 0x448f>,
+			       <&dmac1 0x448e>, <&dmac1 0x448f>,
+			       <&dmac2 0x448e>, <&dmac2 0x448f>,
+			       <&dmac3 0x448e>, <&dmac3 0x448f>,
+			       <&dmac4 0x448e>, <&dmac4 0x448f>;
+			dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
+				    "rx", "tx", "rx", "tx";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		rspi2: spi@12800800 {
+			compatible = "renesas,r9a09g047-rspi", "renesas,r9a09g057-rspi";
+			reg = <0x0 0x12800800 0x0 0x400>;
+			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "idle", "error", "end", "rx", "tx";
+			clocks = <&cpg CPG_MOD 0x5a>,
+				 <&cpg CPG_MOD 0x5b>,
+				 <&cpg CPG_MOD 0x5c>;
+			clock-names = "pclk", "pclk_sfr", "tclk";
+			resets = <&cpg 0x7f>, <&cpg 0x80>;
+			reset-names = "presetn", "tresetn";
+			dmas = <&dmac0 0x4490>, <&dmac0 0x4491>,
+			       <&dmac1 0x4490>, <&dmac1 0x4491>,
+			       <&dmac2 0x4490>, <&dmac2 0x4491>,
+			       <&dmac3 0x4490>, <&dmac3 0x4491>,
+			       <&dmac4 0x4490>, <&dmac4 0x4491>;
+			dma-names = "rx", "tx", "rx", "tx", "rx", "tx",
+				    "rx", "tx", "rx", "tx";
+			power-domains = <&cpg>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		rsci0: serial@12800c00 {
 			compatible = "renesas,r9a09g047-rsci";
 			reg = <0 0x12800c00 0 0x400>;
-- 
2.43.0

Re: [PATCH 4/5] arm64: dts: renesas: r9a09g047: Add RSPI nodes

[Geert Uytterhoeven]

On Tue, 17 Feb 2026 at 17:25, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> Add nodes for the RSPI IPs found in the Renesas RZ/G3E SoC.
>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.1.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 5/5] arm64: dts: renesas: r9a09g047e57-smarc: Enable RSPI0

[Tommaso Merciai]

Enable RSPI0 on RZ/G3E SMARC EVK.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
---
 .../boot/dts/renesas/r9a09g047e57-smarc.dts      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 696903dc7a63..78dcbac8f4e8 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -167,6 +167,13 @@ rsci9_pins: rsci9 {
 		bias-pull-up;
 	};
 
+	rspi0_pins: rspi0 {
+		pinmux = <RZG3E_PORT_PINMUX(M, 4, 2)>, /* MISOA */
+			 <RZG3E_PORT_PINMUX(M, 5, 2)>, /* MOSIA */
+			 <RZG3E_PORT_PINMUX(M, 7, 2)>, /* SSLA0 */
+			 <RZG3E_PORT_PINMUX(M, 6, 2)>; /* RSPCKA */
+	};
+
 	scif_pins: scif {
 		pins = "SCIF_TXD", "SCIF_RXD";
 		renesas,output-impedance = <1>;
@@ -234,6 +241,15 @@ &rsci9 {
 };
 #endif
 
+&rspi0 {
+	pinctrl-0 = <&rspi0_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	status = "okay";
+};
+
 &scif0 {
 	pinctrl-0 = <&scif_pins>;
 	pinctrl-names = "default";
-- 
2.43.0

Re: [PATCH 5/5] arm64: dts: renesas: r9a09g047e57-smarc: Enable RSPI0

[Geert Uytterhoeven]

Hi Tommaso,

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.1.

On Tue, 17 Feb 2026 at 17:25, Tommaso Merciai
<tommaso.merciai.xr@bp.renesas.com> wrote:
> Enable RSPI0 on RZ/G3E SMARC EVK.

which is available on the PMOD0 connector.

> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>

> --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> @@ -167,6 +167,13 @@ rsci9_pins: rsci9 {
>                 bias-pull-up;
>         };
>
> +       rspi0_pins: rspi0 {
> +               pinmux = <RZG3E_PORT_PINMUX(M, 4, 2)>, /* MISOA */
> +                        <RZG3E_PORT_PINMUX(M, 5, 2)>, /* MOSIA */
> +                        <RZG3E_PORT_PINMUX(M, 7, 2)>, /* SSLA0 */
> +                        <RZG3E_PORT_PINMUX(M, 6, 2)>; /* RSPCKA */

I will exchange the last two lines while applying because of sort order.

> +       };
> +
>         scif_pins: scif {
>                 pins = "SCIF_TXD", "SCIF_RXD";
>                 renesas,output-impedance = <1>;

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.1.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: (subset) [PATCH 0/5] Add RSPIs support for RZ/G3E SoC

[Mark Brown]

On Tue, 17 Feb 2026 17:23:44 +0100, Tommaso Merciai wrote:
> Add RSPIs support for RZ/G3E SoC
> 
> Dear All,
> 
> This patch series adds RSPIs support for the Renesas
> RZ/G3E (a.k.a R9A09G047) R9A09G047 SoC.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-7.1

Thanks!

[2/5] spi: dt-bindings: renesas,rzv2h-rspi: Document dmas property
      https://git.kernel.org/broonie/spi/c/c2edd7841f58
[3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support
      https://git.kernel.org/broonie/spi/c/5b7ac8ca0eae

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

Re: [PATCH 0/5] Add RSPIs support for RZ/G3E SoC

[Mark Brown]

On Tue, 17 Feb 2026 17:23:44 +0100, Tommaso Merciai wrote:
> This patch series adds RSPIs support for the Renesas
> RZ/G3E (a.k.a R9A09G047) R9A09G047 SoC.
> 
> Series apply on top of [0].
> 
> [0] https://lore.kernel.org/all/20260128215132.1353381-2-cosmin-gabriel.tanislav.xa@renesas.com/
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/5] clk: renesas: r9a09g047: Add entries for the RSPIs
      (no commit info)
[2/5] spi: dt-bindings: renesas,rzv2h-rspi: Document dmas property
      https://git.kernel.org/broonie/misc/c/c2edd7841f58
[3/5] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support
      https://git.kernel.org/broonie/misc/c/5b7ac8ca0eae
[4/5] arm64: dts: renesas: r9a09g047: Add RSPI nodes
      (no commit info)
[5/5] arm64: dts: renesas: r9a09g047e57-smarc: Enable RSPI0
      (no commit info)

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark