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[95.233.232.76]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-374b5e3511dsm342234f8f.34.2024.08.30.01.21.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 30 Aug 2024 01:21:02 -0700 (PDT) Message-ID: Date: Fri, 30 Aug 2024 10:19:49 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 4/8] dt-bindings: iio: dac: add adi axi-dac bus property To: Conor Dooley Cc: Lars-Peter Clausen , Michael Hennerich , =?UTF-8?Q?Nuno_S=C3=A1?= , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dlechner@baylibre.com References: <20240829-wip-bl-ad3552r-axi-v0-v1-0-b6da6015327a@baylibre.com> <20240829-wip-bl-ad3552r-axi-v0-v1-4-b6da6015327a@baylibre.com> <20240829-stopwatch-morality-a933abb4d688@spud> Content-Language: en-US From: Angelo Dureghello In-Reply-To: <20240829-stopwatch-morality-a933abb4d688@spud> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Conor, On 29/08/24 5:46 PM, Conor Dooley wrote: > On Thu, Aug 29, 2024 at 02:32:02PM +0200, Angelo Dureghello wrote: >> From: Angelo Dureghello >> >> Add bus property. > RFC it may be, but you do need to explain what this bus-type actually > describes for commenting on the suitability of the method to be > meaningful. thanks for the feedbacks, a "bus" is intended as a generic interface connected to the target, may be used from a custom IP (fpga) to communicate with the target device (by read/write(reg and value)) using a special custom interface. The bus could also be physically the same of some well-known existing interfaces (as parallel, lvds or other uncommon interfaces), but using an uncommon/custom protocol over it. In concrete, actually bus-type is added to the backend since the ad3552r DAC chip can be connected (for maximum speed) by a 5 lanes DDR parallel bus (interface that i named QSPI, but it's not exactly a QSPI as a protocol), so it's a device-specific interface. With additions in this patchset, other frontends, of course not only DACs, will be able to add specific busses and read/wrtie to the bus as needed. >> Signed-off-by: Angelo Dureghello >> --- >> Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >> index a55e9bfc66d7..a7ce72e1cd81 100644 >> --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >> +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >> @@ -38,6 +38,15 @@ properties: >> clocks: >> maxItems: 1 > You mentioned about new compatible strings, does the one currently > listed in this binding support both bus types? > > Making the bus type decision based on compatible only really makes sense > if they're different versions of the IP, but not if they're different > configuration options for a given version. > >> + bus-type: DAC IP on fpga actually respects same structure and register set, except for a named "custom" register that may use specific bitfields depending on the application of the IP. > If, as you mentioned, there are multiple bus types, a non-flag property > does make sense. However, I am really not keen on these "forced" numerical > properties at all, I'd much rather see strings used here. ack, thanks. > Thanks, > Conor. thanks a lot, regards, Angelo >> + maxItems: 1 >> + description: | >> + Configure bus type: >> + - 0: none >> + - 1: qspi >> + enum: [0, 1] >> + default: 0 >> + >> '#io-backend-cells': >> const: 0 >> >> >> -- >> 2.45.0.rc1 >> -- ,,, Angelo Dureghello :: :. BayLibre -runtime team- Developer :`___: `____: