[PATCH 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space

[PATCH 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space

[Siddharth Vadapalli]

Hello,

The Cadence PCIe Controllers in TI's K3 SoCs namely:
AM64, J7200, J721E, J721S2 (AM68), J722S, J742S2 and J784S4 (AM69)
support two address regions:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space

Currently, the 128 MB region in the 32-bit address space is enabled in
the device-tree. This might be suitable for most of the use-cases, but
for those use-cases requiring larger address regions than 128 MB it is
necessary to switch to the 64-bit address space with the 4 GB address
region. This series implements the corresponding device-tree changes to
support the 4 GB address region as the default configuration. Existing
use-cases should continue to work without any regression.

Series is based on linux-next tagged next-20250416.

Series has been tested on AM642-EVM, J7200-EVM, J721E-EVM, J721S2-EVM,
J722S-EVM and J784S4-EVM using an NVMe SSD connected to the PCIe
Connector on the EVMs.

Test Logs:
1. AM642-EVM PCIe0
https://gist.github.com/Siddharth-Vadapalli-at-TI/5c3e2e462066ed8a976273db94e856e3
2. J7200-EVM PCIe1
https://gist.github.com/Siddharth-Vadapalli-at-TI/47e1219258b310a1ac0e4a6d7324af33
3. J721E-EVM PCIe0
https://gist.github.com/Siddharth-Vadapalli-at-TI/85abe9ea5032f8e17b2634d616bf0db3
4. J721E-EVM PCIe1
https://gist.github.com/Siddharth-Vadapalli-at-TI/3e42d0f46fe92d353c9a2ae950e4cd64
5. J721S2-EVM PCIe1
https://gist.github.com/Siddharth-Vadapalli-at-TI/7afcf78a6f2601ca9dcf92ca9164be46
6. J722S-EVM PCIe0
https://gist.github.com/Siddharth-Vadapalli-at-TI/6be87d2e2d616db34af0c00b3df66daa
7. J784S4-EVM PCIe0
https://gist.github.com/Siddharth-Vadapalli-at-TI/44f3285756c9f62c7f7d69a10a7b5888

Regards,
Siddharth.

Siddharth Vadapalli (7):
  arm64: dts: ti: k3-am64-main: switch to 64-bit address space for PCIe0
  arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for
    PCIe1
  arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1
  arm64: dts: ti: k3-j721e-main: switch to 64-bit address space for
    PCIe0 and PCIe1
  arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for
    PCIe1
  arm64: dts: ti: k3-j722s-main: switch to 64-bit address space for
    PCIe0
  arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address
    space for PCIe0 and PCIe1

 arch/arm64/boot/dts/ti/k3-am64-main.dtsi           |  7 ++++---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi          |  7 ++++---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi          | 14 ++++++++------
 arch/arm64/boot/dts/ti/k3-j721e.dtsi               |  2 ++
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi         |  7 ++++---
 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi          |  7 ++++---
 .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi  | 14 ++++++++------
 7 files changed, 34 insertions(+), 24 deletions(-)

-- 
2.34.1

[PATCH 1/7] arm64: dts: ti: k3-am64-main: switch to 64-bit address space for PCIe0

[Siddharth Vadapalli]

The PCIe0 instance of PCIe in AM64 SoC supports:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space

The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 324eb44c258d..1a6e5ea65f9a 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1031,7 +1031,7 @@ pcie0_rc: pcie@f102000 {
 		reg = <0x00 0x0f102000 0x00 0x1000>,
 		      <0x00 0x0f100000 0x00 0x400>,
 		      <0x00 0x0d000000 0x00 0x00800000>,
-		      <0x00 0x68000000 0x00 0x00001000>;
+		      <0x06 0x00000000 0x00 0x00001000>;
 		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
@@ -1049,8 +1049,9 @@ pcie0_rc: pcie@f102000 {
 		vendor-id = <0x104c>;
 		device-id = <0xb010>;
 		msi-map = <0x0 &gic_its 0x0 0x10000>;
-		ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
-			 <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
+		ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+			 <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
+			 <0x43000000 0x06 0x08101000 0x06 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
 		status = "disabled";
 	};
-- 
2.34.1

[PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1

[Siddharth Vadapalli]

The PCIe0 instance of PCIe in J7200 SoC supports:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space

The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 5ab510a0605f..e898dffdebbe 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 {
 		reg = <0x00 0x02910000 0x00 0x1000>,
 		      <0x00 0x02917000 0x00 0x400>,
 		      <0x00 0x0d800000 0x00 0x00800000>,
-		      <0x00 0x18000000 0x00 0x00001000>;
+		      <0x41 0x00000000 0x00 0x00001000>;
 		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
@@ -778,8 +778,9 @@ pcie1_rc: pcie@2910000 {
 		device-id = <0xb00f>;
 		msi-map = <0x0 &gic_its 0x0 0x10000>;
 		dma-coherent;
-		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
-			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
+		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
+			 <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 		status = "disabled";
 	};
-- 
2.34.1

Re: [PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1

[Kumar, Udit]

On 4/17/2025 5:34 PM, Siddharth Vadapalli wrote:
> The PCIe0 instance of PCIe in J7200 SoC supports:
> 1. 128 MB address region in the 32-bit address space
> 2. 4 GB address region in the 64-bit address space
>
> The default configuration is that of a 128 MB address region in the
> 32-bit address space. While this might be sufficient for most use-cases,
> it is insufficient for supporting use-cases which require larger address
> spaces. Therefore, switch to using the 64-bit address space with a 4 GB
> address region.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++---
>   1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 5ab510a0605f..e898dffdebbe 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 {
>   		reg = <0x00 0x02910000 0x00 0x1000>,
>   		      <0x00 0x02917000 0x00 0x400>,
>   		      <0x00 0x0d800000 0x00 0x00800000>,
> -		      <0x00 0x18000000 0x00 0x00001000>;
> +		      <0x41 0x00000000 0x00 0x00001000>;
>   		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
>   		interrupt-names = "link_state";
>   		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> @@ -778,8 +778,9 @@ pcie1_rc: pcie@2910000 {
>   		device-id = <0xb00f>;
>   		msi-map = <0x0 &gic_its 0x0 0x10000>;
>   		dma-coherent;
> -		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
> -			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
> +		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
> +			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
> +			 <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */

Sorry for novice question,

with this change,  How do you see  old EP working which supports 32 bit 
addressing,

or some translation is possible ?

0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>

to

0x63000000 0x00 0x08101000 0x41 0x08101000 0x00 0xf7eff000>


>   		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
>   		status = "disabled";
>   	};

Re: [PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1

[Siddharth Vadapalli]

On Sat, Apr 19, 2025 at 11:35:50PM +0530, Kumar, Udit wrote:

Hello Udit,

> 
> On 4/17/2025 5:34 PM, Siddharth Vadapalli wrote:
> > The PCIe0 instance of PCIe in J7200 SoC supports:
> > 1. 128 MB address region in the 32-bit address space
> > 2. 4 GB address region in the 64-bit address space
> > 
> > The default configuration is that of a 128 MB address region in the
> > 32-bit address space. While this might be sufficient for most use-cases,
> > it is insufficient for supporting use-cases which require larger address
> > spaces. Therefore, switch to using the 64-bit address space with a 4 GB
> > address region.
> > 
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > ---
> >   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++---
> >   1 file changed, 4 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > index 5ab510a0605f..e898dffdebbe 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > @@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 {
> >   		reg = <0x00 0x02910000 0x00 0x1000>,
> >   		      <0x00 0x02917000 0x00 0x400>,
> >   		      <0x00 0x0d800000 0x00 0x00800000>,
> > -		      <0x00 0x18000000 0x00 0x00001000>;
> > +		      <0x41 0x00000000 0x00 0x00001000>;
> >   		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> >   		interrupt-names = "link_state";
> >   		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> > @@ -778,8 +778,9 @@ pcie1_rc: pcie@2910000 {
> >   		device-id = <0xb00f>;
> >   		msi-map = <0x0 &gic_its 0x0 0x10000>;
> >   		dma-coherent;
> > -		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
> > -			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
> > +		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
> > +			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
> > +			 <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
> 
> Sorry for novice question,
> 
> with this change,  How do you see  old EP working which supports 32 bit
> addressing,
> 
> or some translation is possible ?
> 
> 0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
> 
> to
> 
> 0x63000000 0x00 0x08101000 0x41 0x08101000 0x00 0xf7eff000>

I didn't understand the question completely, but I shall try to explain
the changes being made which might possibly answer your question.

The ranges property for PCIe is different from the one for other
peripherals and is defined as described at:
https://elinux.org/Device_Tree_Usage#PCI_Address_Translation

With this patch series, the PCIe downstream devices - Switches, Endpoints -
will be assigned IO/Mem regions within the 64-bit CPU address space.

IO and 32-bit Non-Prefetchable MEM regions have the same PCIe Bus
Addresses as before which fall in the 32-bit PCIe Bus Address space.
It is only the newly added 64-bit Prefetchable MEM region that falls in
the 64-bit PCIe Bus Address space.

Please let me know if you require further clarification.

Regards,
Siddharth.

Re: [PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1

[Kumar, Udit]

Hello Siddharth

On 4/20/2025 8:33 AM, Siddharth Vadapalli wrote:
> On Sat, Apr 19, 2025 at 11:35:50PM +0530, Kumar, Udit wrote:
>
> Hello Udit,
>
>> On 4/17/2025 5:34 PM, Siddharth Vadapalli wrote:
>>> The PCIe0 instance of PCIe in J7200 SoC supports:
>>> 1. 128 MB address region in the 32-bit address space
>>> 2. 4 GB address region in the 64-bit address space
>>>
>>> The default configuration is that of a 128 MB address region in the
>>> 32-bit address space. While this might be sufficient for most use-cases,
>>> it is insufficient for supporting use-cases which require larger address
>>> spaces. Therefore, switch to using the 64-bit address space with a 4 GB
>>> address region.
>>>
>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>>> ---
>>>    arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++---
>>>    1 file changed, 4 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>>> index 5ab510a0605f..e898dffdebbe 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>>> @@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 {
>>>    		reg = <0x00 0x02910000 0x00 0x1000>,
>>>    		      <0x00 0x02917000 0x00 0x400>,
>>>    		      <0x00 0x0d800000 0x00 0x00800000>,
>>> -		      <0x00 0x18000000 0x00 0x00001000>;
>>> +		      <0x41 0x00000000 0x00 0x00001000>;
>>>    		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
>>>    		interrupt-names = "link_state";
>>>    		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>>> @@ -778,8 +778,9 @@ pcie1_rc: pcie@2910000 {
>>>    		device-id = <0xb00f>;
>>>    		msi-map = <0x0 &gic_its 0x0 0x10000>;
>>>    		dma-coherent;
>>> -		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
>>> -			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
>>> +		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
>>> +			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
>>> +			 <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
>> Sorry for novice question,
>>
>> with this change,  How do you see  old EP working which supports 32 bit
>> addressing,
>>
>> or some translation is possible ?
>>
>> 0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
>>
>> to
>>
>> 0x63000000 0x00 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
> I didn't understand the question completely, but I shall try to explain
> the changes being made which might possibly answer your question.

If I understood well then what you are doing here

0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>

PCIe address
0x43000000 0x41 0x08101000 -->
Property 0x43
0x43 as npt000ss ->relocatable, prefetch and 64 Bit memory space PCIe Bus address  0x41 0x08101000
CPU address space 0x41 0x08101000
This will work fine, if EP supports 64 bit addressing scheme.

In case, we want to work with EP of 32 Bit, Then do you see , we need to relocate PCIe (lower 32 bits) to CPU address (64 bits)



> The ranges property for PCIe is different from the one for other
> peripherals and is defined as described at:
> https://elinux.org/Device_Tree_Usage#PCI_Address_Translation
>
> With this patch series, the PCIe downstream devices - Switches, Endpoints -
> will be assigned IO/Mem regions within the 64-bit CPU address space.
>
> IO and 32-bit Non-Prefetchable MEM regions have the same PCIe Bus
> Addresses as before which fall in the 32-bit PCIe Bus Address space.
> It is only the newly added 64-bit Prefetchable MEM region that falls in
> the 64-bit PCIe Bus Address space.
>
> Please let me know if you require further clarification.


Sure, will ping you :)


>
> Regards,
> Siddharth.

Re: [PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1

[Siddharth Vadapalli]

On Sun, Apr 20, 2025 at 10:17:46AM +0530, Kumar, Udit wrote:
> Hello Siddharth
> 
> On 4/20/2025 8:33 AM, Siddharth Vadapalli wrote:
> > On Sat, Apr 19, 2025 at 11:35:50PM +0530, Kumar, Udit wrote:
> > 
> > Hello Udit,
> > 
> > > On 4/17/2025 5:34 PM, Siddharth Vadapalli wrote:
> > > > The PCIe0 instance of PCIe in J7200 SoC supports:
> > > > 1. 128 MB address region in the 32-bit address space
> > > > 2. 4 GB address region in the 64-bit address space
> > > > 
> > > > The default configuration is that of a 128 MB address region in the
> > > > 32-bit address space. While this might be sufficient for most use-cases,
> > > > it is insufficient for supporting use-cases which require larger address
> > > > spaces. Therefore, switch to using the 64-bit address space with a 4 GB
> > > > address region.
> > > > 
> > > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > > > ---
> > > >    arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++---
> > > >    1 file changed, 4 insertions(+), 3 deletions(-)
> > > > 
> > > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > > > index 5ab510a0605f..e898dffdebbe 100644
> > > > --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > > > +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > > > @@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 {
> > > >    		reg = <0x00 0x02910000 0x00 0x1000>,
> > > >    		      <0x00 0x02917000 0x00 0x400>,
> > > >    		      <0x00 0x0d800000 0x00 0x00800000>,
> > > > -		      <0x00 0x18000000 0x00 0x00001000>;
> > > > +		      <0x41 0x00000000 0x00 0x00001000>;
> > > >    		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> > > >    		interrupt-names = "link_state";
> > > >    		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> > > > @@ -778,8 +778,9 @@ pcie1_rc: pcie@2910000 {
> > > >    		device-id = <0xb00f>;
> > > >    		msi-map = <0x0 &gic_its 0x0 0x10000>;
> > > >    		dma-coherent;
> > > > -		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
> > > > -			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
> > > > +		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
> > > > +			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
> > > > +			 <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
> > > Sorry for novice question,
> > > 
> > > with this change,  How do you see  old EP working which supports 32 bit
> > > addressing,
> > > 
> > > or some translation is possible ?
> > > 
> > > 0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
> > > 
> > > to
> > > 
> > > 0x63000000 0x00 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
> > I didn't understand the question completely, but I shall try to explain
> > the changes being made which might possibly answer your question.
> 
> If I understood well then what you are doing here
> 
> 0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
> 
> PCIe address
> 0x43000000 0x41 0x08101000 -->
> Property 0x43
> 0x43 as npt000ss ->relocatable, prefetch and 64 Bit memory space PCIe Bus address  0x41 0x08101000
> CPU address space 0x41 0x08101000
> This will work fine, if EP supports 64 bit addressing scheme.
> 
> In case, we want to work with EP of 32 Bit, Then do you see , we need to relocate PCIe (lower 32 bits) to CPU address (64 bits)

A total of 3 Address Regions have been defined:
1. 1 MB IO in the 32-bit PCIe Bus Address Space
2. 128 MB Non-Prefetchable MEM in the 32-bit PCIe Bus Address Space
3. (4 GB - 129 MB - 4 KB) Prefetchable MEM in the 64-bit PCIe Bus
Address Space

'1' and '2' above provide backward compatibility with Endpoint Devices
that can only support 32-bit PCIe Bus Addressing. The __newly__ added
'3' enables Endpoint Devices that support 64-bit PCIe Bus Addressing to
claim larger Memory Address Space on top of what is supported by '1' and
'2'.

Regards,
Siddharth.

Re: [PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1

[Kumar, Udit]

On 4/20/2025 7:48 PM, Siddharth Vadapalli wrote:
> On Sun, Apr 20, 2025 at 10:17:46AM +0530, Kumar, Udit wrote:
>> Hello Siddharth
>>
>> On 4/20/2025 8:33 AM, Siddharth Vadapalli wrote:
>>> On Sat, Apr 19, 2025 at 11:35:50PM +0530, Kumar, Udit wrote:
>>>
>>> Hello Udit,
>>>
>>>> On 4/17/2025 5:34 PM, Siddharth Vadapalli wrote:
>>>>> The PCIe0 instance of PCIe in J7200 SoC supports:
>>>>> 1. 128 MB address region in the 32-bit address space
>>>>> 2. 4 GB address region in the 64-bit address space
>>>>>
>>>>> The default configuration is that of a 128 MB address region in the
>>>>> 32-bit address space. While this might be sufficient for most use-cases,
>>>>> it is insufficient for supporting use-cases which require larger address
>>>>> spaces. Therefore, switch to using the 64-bit address space with a 4 GB
>>>>> address region.
>>>>>
>>>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>>>>> ---
>>>>>     arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++---
>>>>>     1 file changed, 4 insertions(+), 3 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>>>>> index 5ab510a0605f..e898dffdebbe 100644
>>>>> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>>>>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
>>>>> @@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 {
>>>>>     		reg = <0x00 0x02910000 0x00 0x1000>,
>>>>>     		      <0x00 0x02917000 0x00 0x400>,
>>>>>     		      <0x00 0x0d800000 0x00 0x00800000>,
>>>>> -		      <0x00 0x18000000 0x00 0x00001000>;
>>>>> +		      <0x41 0x00000000 0x00 0x00001000>;
>>>>>     		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
>>>>>     		interrupt-names = "link_state";
>>>>>     		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>>>>> @@ -778,8 +778,9 @@ pcie1_rc: pcie@2910000 {
>>>>>     		device-id = <0xb00f>;
>>>>>     		msi-map = <0x0 &gic_its 0x0 0x10000>;
>>>>>     		dma-coherent;
>>>>> -		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
>>>>> -			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
>>>>> +		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
>>>>> +			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
>>>>> +			 <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
>>>> Sorry for novice question,
>>>>
>>>> with this change,  How do you see  old EP working which supports 32 bit
>>>> addressing,
>>>>
>>>> or some translation is possible ?
>>>>
>>>> 0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
>>>>
>>>> to
>>>>
>>>> 0x63000000 0x00 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
>>> I didn't understand the question completely, but I shall try to explain
>>> the changes being made which might possibly answer your question.
>> If I understood well then what you are doing here
>>
>> 0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
>>
>> PCIe address
>> 0x43000000 0x41 0x08101000 -->
>> Property 0x43
>> 0x43 as npt000ss ->relocatable, prefetch and 64 Bit memory space PCIe Bus address  0x41 0x08101000
>> CPU address space 0x41 0x08101000
>> This will work fine, if EP supports 64 bit addressing scheme.
>>
>> In case, we want to work with EP of 32 Bit, Then do you see , we need to relocate PCIe (lower 32 bits) to CPU address (64 bits)
> A total of 3 Address Regions have been defined:
> 1. 1 MB IO in the 32-bit PCIe Bus Address Space
> 2. 128 MB Non-Prefetchable MEM in the 32-bit PCIe Bus Address Space
> 3. (4 GB - 129 MB - 4 KB) Prefetchable MEM in the 64-bit PCIe Bus
> Address Space
>
> '1' and '2' above provide backward compatibility with Endpoint Devices
> that can only support 32-bit PCIe Bus Addressing. The __newly__ added
> '3' enables Endpoint Devices that support 64-bit PCIe Bus Addressing to
> claim larger Memory Address Space on top of what is supported by '1' and
> '2'.

Thanks Siddharth,

I understand, you are enabling 64 bit addressing, keeping previous 
addressing scheme unchanged.

Since, you are changing, it will be good to give max possible addresses 
for 32 bits EP.

or

If you are saying , 32 bit EP has to be limited to 128MB then

Acked-by: Udit Kumar <u-kumar1@ti.com>

> Regards,
> Siddharth.

Re: [PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1

[Siddharth Vadapalli]

On Mon, Apr 21, 2025 at 01:29:47PM +0530, Kumar, Udit wrote:
> 
> On 4/20/2025 7:48 PM, Siddharth Vadapalli wrote:
> > On Sun, Apr 20, 2025 at 10:17:46AM +0530, Kumar, Udit wrote:
> > > Hello Siddharth
> > > 
> > > On 4/20/2025 8:33 AM, Siddharth Vadapalli wrote:
> > > > On Sat, Apr 19, 2025 at 11:35:50PM +0530, Kumar, Udit wrote:
> > > > 
> > > > Hello Udit,
> > > > 
> > > > > On 4/17/2025 5:34 PM, Siddharth Vadapalli wrote:
> > > > > > The PCIe0 instance of PCIe in J7200 SoC supports:
> > > > > > 1. 128 MB address region in the 32-bit address space
> > > > > > 2. 4 GB address region in the 64-bit address space
> > > > > > 
> > > > > > The default configuration is that of a 128 MB address region in the
> > > > > > 32-bit address space. While this might be sufficient for most use-cases,
> > > > > > it is insufficient for supporting use-cases which require larger address
> > > > > > spaces. Therefore, switch to using the 64-bit address space with a 4 GB
> > > > > > address region.
> > > > > > 
> > > > > > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > > > > > ---
> > > > > >     arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++---
> > > > > >     1 file changed, 4 insertions(+), 3 deletions(-)
> > > > > > 
> > > > > > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > > > > > index 5ab510a0605f..e898dffdebbe 100644
> > > > > > --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > > > > > +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > > > > > @@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 {
> > > > > >     		reg = <0x00 0x02910000 0x00 0x1000>,
> > > > > >     		      <0x00 0x02917000 0x00 0x400>,
> > > > > >     		      <0x00 0x0d800000 0x00 0x00800000>,
> > > > > > -		      <0x00 0x18000000 0x00 0x00001000>;
> > > > > > +		      <0x41 0x00000000 0x00 0x00001000>;
> > > > > >     		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> > > > > >     		interrupt-names = "link_state";
> > > > > >     		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> > > > > > @@ -778,8 +778,9 @@ pcie1_rc: pcie@2910000 {
> > > > > >     		device-id = <0xb00f>;
> > > > > >     		msi-map = <0x0 &gic_its 0x0 0x10000>;
> > > > > >     		dma-coherent;
> > > > > > -		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
> > > > > > -			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
> > > > > > +		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
> > > > > > +			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
> > > > > > +			 <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
> > > > > Sorry for novice question,
> > > > > 
> > > > > with this change,  How do you see  old EP working which supports 32 bit
> > > > > addressing,
> > > > > 
> > > > > or some translation is possible ?
> > > > > 
> > > > > 0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
> > > > > 
> > > > > to
> > > > > 
> > > > > 0x63000000 0x00 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
> > > > I didn't understand the question completely, but I shall try to explain
> > > > the changes being made which might possibly answer your question.
> > > If I understood well then what you are doing here
> > > 
> > > 0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
> > > 
> > > PCIe address
> > > 0x43000000 0x41 0x08101000 -->
> > > Property 0x43
> > > 0x43 as npt000ss ->relocatable, prefetch and 64 Bit memory space PCIe Bus address  0x41 0x08101000
> > > CPU address space 0x41 0x08101000
> > > This will work fine, if EP supports 64 bit addressing scheme.
> > > 
> > > In case, we want to work with EP of 32 Bit, Then do you see , we need to relocate PCIe (lower 32 bits) to CPU address (64 bits)
> > A total of 3 Address Regions have been defined:
> > 1. 1 MB IO in the 32-bit PCIe Bus Address Space
> > 2. 128 MB Non-Prefetchable MEM in the 32-bit PCIe Bus Address Space
> > 3. (4 GB - 129 MB - 4 KB) Prefetchable MEM in the 64-bit PCIe Bus
> > Address Space
> > 
> > '1' and '2' above provide backward compatibility with Endpoint Devices
> > that can only support 32-bit PCIe Bus Addressing. The __newly__ added
> > '3' enables Endpoint Devices that support 64-bit PCIe Bus Addressing to
> > claim larger Memory Address Space on top of what is supported by '1' and
> > '2'.
> 
> Thanks Siddharth,
> 
> I understand, you are enabling 64 bit addressing, keeping previous
> addressing scheme unchanged.
> 
> Since, you are changing, it will be good to give max possible addresses for
> 32 bits EP.
> 
> or
> 
> If you are saying , 32 bit EP has to be limited to 128MB then

Based on the offline discussion, since the total address region is 4 GB,
and given that all of it is addressable in the 32-bit PCIe Bus Address
Space, I will update the patch series to allocate the 4 GB region as:
1. 1MB IO in the 32-bit PCIe Bus Address Space
2. (4GB - 1MB - 4KB) Non-Prefetchable MEM in the 32-bit PCIe Bus Address
   Space

Regards,
Siddharth.

[PATCH 3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1

[Siddharth Vadapalli]

The PCIe0 DAT1 and PCIe1 DAT1 are 4 GB address regions in the 64-bit
address space of the respective PCIe Controllers. Hence, update the
ranges to include them.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index a7f2f52f42f7..4f5d277c97a4 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -126,6 +126,8 @@ cbass_main: bus@100000 {
 			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
 			 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
 			 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
+			 <0x40 0x00000000 0x40 0x00000000 0x00 0x08000000>, /* PCIe0 DAT1 */
+			 <0x41 0x00000000 0x41 0x00000000 0x00 0x08000000>, /* PCIe1 DAT1 */
 			 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
 			 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
 			 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
-- 
2.34.1

Re: [PATCH 3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1

[Kumar, Udit]

On 4/17/2025 5:34 PM, Siddharth Vadapalli wrote:
> The PCIe0 DAT1 and PCIe1 DAT1 are 4 GB address regions in the 64-bit
> address space of the respective PCIe Controllers. Hence, update the
> ranges to include them.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> index a7f2f52f42f7..4f5d277c97a4 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> @@ -126,6 +126,8 @@ cbass_main: bus@100000 {
>   			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
>   			 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
>   			 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
> +			 <0x40 0x00000000 0x40 0x00000000 0x00 0x08000000>, /* PCIe0 DAT1 */
> +			 <0x41 0x00000000 0x41 0x00000000 0x00 0x08000000>, /* PCIe1 DAT1 */

Do you want to map whole 4GB or just 128M ?


>   			 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
>   			 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
>   			 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */

Re: [PATCH 3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1

[Siddharth Vadapalli]

On Sat, Apr 19, 2025 at 11:39:55PM +0530, Kumar, Udit wrote:

Hello Udit,

> 
> On 4/17/2025 5:34 PM, Siddharth Vadapalli wrote:
> > The PCIe0 DAT1 and PCIe1 DAT1 are 4 GB address regions in the 64-bit
> > address space of the respective PCIe Controllers. Hence, update the
> > ranges to include them.
> > 
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > ---
> >   arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 ++
> >   1 file changed, 2 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> > index a7f2f52f42f7..4f5d277c97a4 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> > @@ -126,6 +126,8 @@ cbass_main: bus@100000 {
> >   			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
> >   			 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
> >   			 <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
> > +			 <0x40 0x00000000 0x40 0x00000000 0x00 0x08000000>, /* PCIe0 DAT1 */
> > +			 <0x41 0x00000000 0x41 0x00000000 0x00 0x08000000>, /* PCIe1 DAT1 */
> 
> Do you want to map whole 4GB or just 128M ?

It should have been 4 GB and needs to be updated. Thank you for
reviewing the patch and pointing this out. I will fix this in the next
version of the series.

Regards,
Siddharth.

[PATCH 4/7] arm64: dts: ti: k3-j721e-main: switch to 64-bit address space for PCIe0 and PCIe1

[Siddharth Vadapalli]

The PCIe0 and PCIe1 instances of PCIe in J721E SoC support:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space

The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index af3d730154ac..8bd5cf26fc42 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -941,7 +941,7 @@ pcie0_rc: pcie@2900000 {
 		reg = <0x00 0x02900000 0x00 0x1000>,
 		      <0x00 0x02907000 0x00 0x400>,
 		      <0x00 0x0d000000 0x00 0x00800000>,
-		      <0x00 0x10000000 0x00 0x00001000>;
+		      <0x40 0x00000000 0x00 0x00001000>;
 		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
@@ -959,8 +959,9 @@ pcie0_rc: pcie@2900000 {
 		device-id = <0xb00d>;
 		msi-map = <0x0 &gic_its 0x0 0x10000>;
 		dma-coherent;
-		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
-			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
+		ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+			 <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
+			 <0x43000000 0x40 0x08101000 0x40 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 		status = "disabled";
 	};
@@ -970,7 +971,7 @@ pcie1_rc: pcie@2910000 {
 		reg = <0x00 0x02910000 0x00 0x1000>,
 		      <0x00 0x02917000 0x00 0x400>,
 		      <0x00 0x0d800000 0x00 0x00800000>,
-		      <0x00 0x18000000 0x00 0x00001000>;
+		      <0x41 0x00000000 0x00 0x00001000>;
 		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
@@ -988,8 +989,9 @@ pcie1_rc: pcie@2910000 {
 		device-id = <0xb00d>;
 		msi-map = <0x0 &gic_its 0x10000 0x10000>;
 		dma-coherent;
-		ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
-			 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
+		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
+			 <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 		status = "disabled";
 	};
-- 
2.34.1

[PATCH 5/7] arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for PCIe1

[Siddharth Vadapalli]

The PCIe1 instance of PCIe in J721S2 SoC supports:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space

The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 92bf48fdbeba..da2fe83ddcf7 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -1394,7 +1394,7 @@ pcie1_rc: pcie@2910000 {
 		reg = <0x00 0x02910000 0x00 0x1000>,
 		      <0x00 0x02917000 0x00 0x400>,
 		      <0x00 0x0d800000 0x00 0x800000>,
-		      <0x00 0x18000000 0x00 0x1000>;
+		      <0x41 0x00000000 0x00 0x1000>;
 		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
@@ -1412,8 +1412,9 @@ pcie1_rc: pcie@2910000 {
 		device-id = <0xb013>;
 		msi-map = <0x0 &gic_its 0x0 0x10000>;
 		dma-coherent;
-		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
-			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
+		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
+			 <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 		#interrupt-cells = <1>;
 		interrupt-map-mask = <0 0 0 7>;
-- 
2.34.1

[PATCH 6/7] arm64: dts: ti: k3-j722s-main: switch to 64-bit address space for PCIe0

[Siddharth Vadapalli]

The PCIe0 instance of PCIe in J722S SoC supports:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space

The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 6850f50530f1..a3928fe63ae4 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -98,10 +98,11 @@ pcie0_rc: pcie@f102000 {
 		reg = <0x00 0x0f102000 0x00 0x1000>,
 		      <0x00 0x0f100000 0x00 0x400>,
 		      <0x00 0x0d000000 0x00 0x00800000>,
-		      <0x00 0x68000000 0x00 0x00001000>;
+		      <0x06 0x00000000 0x00 0x00001000>;
 		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
-		ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
-			 <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
+		ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+			 <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
+			 <0x43000000 0x06 0x08101000 0x06 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
-- 
2.34.1

[PATCH 7/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address space for PCIe0 and PCIe1

[Siddharth Vadapalli]

The PCIe0 and PCIe1 instances of PCIe in J742S2 and J784S4 SoCs support:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space

The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
 .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi  | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index 1944616ab357..0cbf0fba9112 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -1055,7 +1055,7 @@ pcie0_rc: pcie@2900000 {
 		reg = <0x00 0x02900000 0x00 0x1000>,
 		      <0x00 0x02907000 0x00 0x400>,
 		      <0x00 0x0d000000 0x00 0x00800000>,
-		      <0x00 0x10000000 0x00 0x00001000>;
+		      <0x40 0x00000000 0x00 0x00001000>;
 		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
@@ -1073,8 +1073,9 @@ pcie0_rc: pcie@2900000 {
 		device-id = <0xb012>;
 		msi-map = <0x0 &gic_its 0x0 0x10000>;
 		dma-coherent;
-		ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
-			 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
+		ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+			 <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
+			 <0x43000000 0x40 0x08101000 0x40 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 		status = "disabled";
 	};
@@ -1084,7 +1085,7 @@ pcie1_rc: pcie@2910000 {
 		reg = <0x00 0x02910000 0x00 0x1000>,
 		      <0x00 0x02917000 0x00 0x400>,
 		      <0x00 0x0d800000 0x00 0x00800000>,
-		      <0x00 0x18000000 0x00 0x00001000>;
+		      <0x41 0x00000000 0x00 0x00001000>;
 		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
 		interrupt-names = "link_state";
 		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
@@ -1102,8 +1103,9 @@ pcie1_rc: pcie@2910000 {
 		device-id = <0xb012>;
 		msi-map = <0x0 &gic_its 0x10000 0x10000>;
 		dma-coherent;
-		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
-			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
+		ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+			 <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
+			 <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
 		status = "disabled";
 	};
-- 
2.34.1