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Tue, 31 Dec 2024 12:01:53 +0000 (GMT) Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BVC1r6G027202 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 31 Dec 2024 12:01:53 GMT Received: from [10.216.1.202] (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 31 Dec 2024 04:01:45 -0800 Message-ID: Date: Tue, 31 Dec 2024 17:31:41 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH v5 6/6] arm64: dts: qcom: Enable cpu cooling devices for QCS9075 platforms To: Dmitry Baryshkov , Wasim Nazir CC: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , References: <20241229152332.3068172-1-quic_wasimn@quicinc.com> <20241229152332.3068172-7-quic_wasimn@quicinc.com> From: Manaf Meethalavalappu Pallikunhi In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: jvcTLdb5cAEdRliB9N-SDLCBvzwn5B5P X-Proofpoint-GUID: jvcTLdb5cAEdRliB9N-SDLCBvzwn5B5P X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 phishscore=0 clxscore=1011 mlxlogscore=797 mlxscore=0 bulkscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412310102 Hi Dmitry, On 12/30/2024 9:10 PM, Dmitry Baryshkov wrote: > On Sun, Dec 29, 2024 at 08:53:32PM +0530, Wasim Nazir wrote: >> From: Manaf Meethalavalappu Pallikunhi >> >> In QCS9100 SoC, the safety subsystem monitors all thermal sensors and >> does corrective action for each subsystem based on sensor violation >> to comply safety standards. But as QCS9075 is non-safe SoC it >> requires conventional thermal mitigation to control thermal for >> different subsystems. >> >> The cpu frequency throttling for different cpu tsens is enabled in >> hardware as first defense for cpu thermal control. But QCS9075 SoC >> has higher ambient specification. During high ambient condition, even >> lowest frequency with multi cores can slowly build heat over the time >> and it can lead to thermal run-away situations. This patch restrict >> cpu cores during this scenario helps further thermal control and >> avoids thermal critical violation. >> >> Add cpu idle injection cooling bindings for cpu tsens thermal zones >> as a mitigation for cpu subsystem prior to thermal shutdown. >> >> Add cpu frequency cooling devices that will be used by userspace >> thermal governor to mitigate skin thermal management. > Does anything prevent us from having this config as a part of the basic > sa8775p.dtsi setup? If HW is present in the base version but it is not > accessible for whatever reason, please move it the base device config > and use status "disabled" or "reserved" to the respective board files. Sure,  I will move idle injection node for each cpu to sa8775p.dtsi and keep it disabled state. #cooling cells property for CPU, still wanted to keep it in board files as we don't want to enable any cooling device in base DT. Best Regards, Manaf > >> Signed-off-by: Manaf Meethalavalappu Pallikunhi >> --- >> arch/arm64/boot/dts/qcom/qcs9075-rb8.dts | 1 + >> arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts | 1 + >> arch/arm64/boot/dts/qcom/qcs9075-ride.dts | 1 + >> arch/arm64/boot/dts/qcom/qcs9075-thermal.dtsi | 287 ++++++++++++++++++ >> 4 files changed, 290 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/qcs9075-thermal.dtsi >> >> diff --git a/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts b/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts >> index ecaa383b6508..3ab6deeaacf1 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs9075-rb8.dts >> @@ -9,6 +9,7 @@ >> >> #include "sa8775p.dtsi" >> #include "sa8775p-pmics.dtsi" >> +#include "qcs9075-thermal.dtsi" >> >> / { >> model = "Qualcomm Technologies, Inc. Robotics RB8"; >> diff --git a/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts b/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts >> index d9a8956d3a76..5f2d9f416617 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs9075-ride-r3.dts >> @@ -5,6 +5,7 @@ >> /dts-v1/; >> >> #include "sa8775p-ride.dtsi" >> +#include "qcs9075-thermal.dtsi" >> >> / { >> model = "Qualcomm Technologies, Inc. QCS9075 Ride Rev3"; >> diff --git a/arch/arm64/boot/dts/qcom/qcs9075-ride.dts b/arch/arm64/boot/dts/qcom/qcs9075-ride.dts >> index 3b524359a72d..10ce48e7ba2f 100644 >> --- a/arch/arm64/boot/dts/qcom/qcs9075-ride.dts >> +++ b/arch/arm64/boot/dts/qcom/qcs9075-ride.dts >> @@ -5,6 +5,7 @@ >> /dts-v1/; >> >> #include "sa8775p-ride.dtsi" >> +#include "qcs9075-thermal.dtsi" >> >> / { >> model = "Qualcomm Technologies, Inc. QCS9075 Ride"; >> diff --git a/arch/arm64/boot/dts/qcom/qcs9075-thermal.dtsi b/arch/arm64/boot/dts/qcom/qcs9075-thermal.dtsi >> new file mode 100644 >> index 000000000000..40544c8582c4 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/qcs9075-thermal.dtsi >> @@ -0,0 +1,287 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#include >> + >> +&cpu0 { >> + #cooling-cells = <2>; >> +}; >> + >> +&cpu1 { >> + #cooling-cells = <2>; >> + cpu1_idle: thermal-idle { >> + #cooling-cells = <2>; >> + duration-us = <800000>; >> + exit-latency-us = <10000>; >> + }; >> +}; >> + >> +&cpu2 { >> + #cooling-cells = <2>; >> + cpu2_idle: thermal-idle { >> + #cooling-cells = <2>; >> + duration-us = <800000>; >> + exit-latency-us = <10000>; >> + }; >> +}; >> + >> +&cpu3 { >> + #cooling-cells = <2>; >> + cpu3_idle: thermal-idle { >> + #cooling-cells = <2>; >> + duration-us = <800000>; >> + exit-latency-us = <10000>; >> + }; >> +}; >> + >> +&cpu4 { >> + #cooling-cells = <2>; >> + cpu4_idle: thermal-idle { >> + #cooling-cells = <2>; >> + duration-us = <800000>; >> + exit-latency-us = <10000>; >> + }; >> +}; >> + >> +&cpu5 { >> + #cooling-cells = <2>; >> + cpu5_idle: thermal-idle { >> + #cooling-cells = <2>; >> + duration-us = <800000>; >> + exit-latency-us = <10000>; >> + }; >> +}; >> + >> +&cpu6 { >> + #cooling-cells = <2>; >> + cpu6_idle: thermal-idle { >> + #cooling-cells = <2>; >> + duration-us = <800000>; >> + exit-latency-us = <10000>; >> + }; >> +}; >> + >> +&cpu7 { >> + #cooling-cells = <2>; >> + cpu7_idle: thermal-idle { >> + #cooling-cells = <2>; >> + duration-us = <800000>; >> + exit-latency-us = <10000>; >> + }; >> +}; >> + >> +/ { >> + thermal-zones { >> + cpu-0-1-0-thermal { >> + trips { >> + cpu_0_1_0_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_0_1_0_passive>; >> + cooling-device = <&cpu1_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-0-2-0-thermal { >> + trips { >> + cpu_0_2_0_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_0_2_0_passive>; >> + cooling-device = <&cpu2_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-0-3-0-thermal { >> + trips { >> + cpu_0_3_0_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_0_3_0_passive>; >> + cooling-device = <&cpu3_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-0-1-1-thermal { >> + trips { >> + cpu_0_1_1_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_0_1_1_passive>; >> + cooling-device = <&cpu1_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-0-2-1-thermal { >> + trips { >> + cpu_0_2_1_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_0_2_1_passive>; >> + cooling-device = <&cpu2_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-0-3-1-thermal { >> + trips { >> + cpu_0_3_1_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_0_3_1_passive>; >> + cooling-device = <&cpu3_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-1-0-0-thermal { >> + trips { >> + cpu_1_0_0_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_1_0_0_passive>; >> + cooling-device = <&cpu4_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-1-1-0-thermal { >> + trips { >> + cpu_1_1_0_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_1_1_0_passive>; >> + cooling-device = <&cpu5_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-1-2-0-thermal { >> + trips { >> + cpu_1_2_0_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_1_2_0_passive>; >> + cooling-device = <&cpu6_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-1-3-0-thermal { >> + trips { >> + cpu_1_3_0_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_1_3_0_passive>; >> + cooling-device = <&cpu7_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-1-0-1-thermal { >> + trips { >> + cpu_1_0_1_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_1_0_1_passive>; >> + cooling-device = <&cpu4_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-1-1-1-thermal { >> + trips { >> + cpu_1_1_1_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_1_1_1_passive>; >> + cooling-device = <&cpu5_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-1-2-1-thermal { >> + trips { >> + cpu_1_2_1_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_1_2_1_passive>; >> + cooling-device = <&cpu6_idle 100 100>; >> + }; >> + }; >> + }; >> + >> + cpu-1-3-1-thermal { >> + trips { >> + cpu_1_3_1_passive: trip-point1 { >> + temperature = <116000>; >> + }; >> + }; >> + >> + cooling-maps { >> + map0 { >> + trip = <&cpu_1_3_1_passive>; >> + cooling-device = <&cpu7_idle 100 100>; >> + }; >> + }; >> + }; >> + }; >> +}; >> -- >> 2.47.0 >>