From: <Daire.McNamara@microchip.com>
To: <linux-riscv@lists.infradead.org>, <kw@linux.com>,
<Conor.Dooley@microchip.com>, <devicetree@vger.kernel.org>,
<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>, <lpieralisi@kernel.org>,
<linux-pci@vger.kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <bhelgaas@google.com>
Subject: Re: [PATCH v3 00/11] PCI: microchip: Partition address translations
Date: Tue, 31 Jan 2023 17:03:00 +0000 [thread overview]
Message-ID: <d5a5ba3b01953c9db435f2371adee6e2b61d26dd.camel@microchip.com> (raw)
In-Reply-To: <20230111125323.1911373-1-daire.mcnamara@microchip.com>
Hi all,
Just touching base here. Can I take it that things are in-hand, and
this patchset is moving into the kernel or is there something I need to
do at my end?
best regards
daire
On Wed, 2023-01-11 at 12:53 +0000, daire.mcnamara@microchip.com wrote:
> From: Daire McNamara <daire.mcnamara@microchip.com>
>
> Changes since v2:
> - Replaced GENMASK(63,0) with GENMASK_ULL(63,0) to remove warning
> - Added patch to avoid warning on cast of argument to
> devm_add_action_or_reset()
> - Added patch to enable building driver as a module
>
> Changes since v1:
> - Removed unused variables causing compile warnings
> - Removed incorrect Signed-off-by: tags
> - Capitalised msi and msi-x
> - Capitalised FIC and respelled busses to buses
> - Capitalised all comments
> - Renamed fabric inter connect to Fabric Interface Controller as per
> PolarFire SoC TRM
>
> Microchip PolarFire SoC is a 64-bit device and has DDR starting at
> 0x80000000 and 0x1000000000. Its PCIe rootport is connected to the
> CPU
> Coreplex via an FPGA fabric. The AXI connections between the Coreplex
> and
> the fabric are 64-bit and the AXI connections between the fabric and
> the
> rootport are 32-bit. For the CPU CorePlex to act as an AXI-Master to
> the
> PCIe devices and for the PCIe devices to act as bus masters to DDR at
> these
> base addresses, the fabric can be customised to add/remove offsets
> for bits
> 38-32 in each direction. These offsets, if present, vary with each
> customer's design.
>
> To support this variety, the rootport driver must know how much
> address
> translation (both inbound and outbound) is performed by a particular
> customer design and how much address translation must be provided by
> the
> rootport.
>
> This patchset contains a parent/child dma-ranges scheme suggested by
> Rob
> Herring. It creates an FPGA PCIe parent bus which wraps the PCIe
> rootport
> and implements a parsing scheme where the root port identifies what
> address
> translations are performed by the FPGA fabric parent bus, and what
> address translations must be done by the rootport itself.
>
> See
> https://lore.kernel.org/linux-pci/20220902142202.2437658-1-daire.mcnamara@microchip.com/
> for the relevant previous patch submission discussion.
>
> It also re-partitions the probe() and init() functions as suggested
> by
> Bjorn Helgaas to make them more maintainable as the init() function
> had
> become too large.
>
> It also contains some minor fixes and clean-ups that are pre-
> requisites:
> - to align register, offset, and mask names with the hardware
> documentation
> and to have the register definitions appear in the same order as in
> the
> hardware documentation;
> - to harvest the MSI information from the hardware configuration
> register
> as these depend on the FPGA fabric design and can vary with
> different
> customer designs;
> - to clean up interrupt initialisation to make it more maintainable;
> - to fix SEC and DED interrupt handling.
>
> I expect Conor will take the dts patch via the soc tree once the PCIe
> parts
> of the series are accepted.
>
> Conor Dooley (1):
> riscv: dts: microchip: add parent ranges and dma-ranges for IKRD
> v2022.09
>
> Daire McNamara (10):
> PCI: microchip: Correct the DED and SEC interrupt bit offsets
> PCI: microchip: Remove cast warning for devm_add_action_or_reset()
> arg
> PCI: microchip: enable building this driver as a module
> PCI: microchip: Align register, offset, and mask names with hw docs
> PCI: microchip: Enable event handlers to access bridge and ctrl
> ptrs
> PCI: microchip: Clean up initialisation of interrupts
> PCI: microchip: Gather MSI information from hardware config
> registers
> PCI: microchip: Re-partition code between probe() and init()
> PCI: microchip: Partition outbound address translation
> PCI: microchip: Partition inbound address translation
>
> .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 62 +-
> drivers/pci/controller/Kconfig | 2 +-
> drivers/pci/controller/pcie-microchip-host.c | 688 +++++++++++++---
> --
> 3 files changed, 533 insertions(+), 219 deletions(-)
>
>
> base-commit: 3c1f24109dfc4fb1a3730ed237e50183c6bb26b3
next prev parent reply other threads:[~2023-01-31 17:03 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-11 12:53 [PATCH v3 00/11] PCI: microchip: Partition address translations daire.mcnamara
2023-01-11 12:53 ` [PATCH v3 01/11] PCI: microchip: Correct the DED and SEC interrupt bit offsets daire.mcnamara
2023-01-11 12:53 ` [PATCH v3 02/11] PCI: microchip: Remove cast warning for devm_add_action_or_reset() arg daire.mcnamara
2023-01-11 18:18 ` Conor Dooley
2023-01-11 12:53 ` [PATCH v3 03/11] PCI: microchip: enable building this driver as a module daire.mcnamara
2023-01-11 17:25 ` Uwe Kleine-König
2023-01-11 18:20 ` Conor Dooley
2023-01-11 12:53 ` [PATCH v3 04/11] PCI: microchip: Align register, offset, and mask names with hw docs daire.mcnamara
2023-01-11 12:53 ` [PATCH v3 05/11] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs daire.mcnamara
2023-01-11 12:53 ` [PATCH v3 06/11] PCI: microchip: Clean up initialisation of interrupts daire.mcnamara
2023-01-11 12:53 ` [PATCH v3 07/11] PCI: microchip: Gather MSI information from hardware config registers daire.mcnamara
2023-02-02 11:45 ` Lorenzo Pieralisi
2023-01-11 12:53 ` [PATCH v3 08/11] PCI: microchip: Re-partition code between probe() and init() daire.mcnamara
2023-01-11 12:53 ` [PATCH v3 09/11] PCI: microchip: Partition outbound address translation daire.mcnamara
2023-02-02 11:28 ` Lorenzo Pieralisi
2023-01-11 12:53 ` [PATCH v3 10/11] PCI: microchip: Partition inbound " daire.mcnamara
2023-02-02 11:31 ` Lorenzo Pieralisi
2023-02-02 12:13 ` Robin Murphy
2023-01-11 12:53 ` [PATCH v3 11/11] riscv: dts: microchip: add parent ranges and dma-ranges for IKRD v2022.09 daire.mcnamara
2023-01-20 11:07 ` [PATCH v3 00/11] PCI: microchip: Partition address translations Conor Dooley
2023-01-31 17:03 ` Daire.McNamara [this message]
2023-02-02 11:02 ` Lorenzo Pieralisi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=d5a5ba3b01953c9db435f2371adee6e2b61d26dd.camel@microchip.com \
--to=daire.mcnamara@microchip.com \
--cc=Conor.Dooley@microchip.com \
--cc=aou@eecs.berkeley.edu \
--cc=bhelgaas@google.com \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kw@linux.com \
--cc=linux-pci@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=lpieralisi@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).