From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0489FC07E9B for ; Tue, 20 Jul 2021 05:17:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DCDFB6113C for ; Tue, 20 Jul 2021 05:17:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238381AbhGTEgP (ORCPT ); Tue, 20 Jul 2021 00:36:15 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:47904 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232389AbhGTEgJ (ORCPT ); Tue, 20 Jul 2021 00:36:09 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 16K5GhDX016679; Tue, 20 Jul 2021 00:16:43 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1626758203; bh=UplAe3t8SLLOOhAg9JAaaBmoK8p03dxzvhQatg+1xZE=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=FcQUnV/JItYL16BZGJteMfBNbuCiytcNfGR59xUbIwcB7B5FtuItw+lcsUmKHbcJ6 toxlS3j/r1oQDGJzL+r+RR7EXk0eMRYRbLlYXViRBw4MWhw4kQrv7x0OomzqqtD7JB wSFtOeT/s4+fMpfUSu31az3pOY/ZOPzLVgil9pJ4= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 16K5GhDD065983 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 20 Jul 2021 00:16:43 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Tue, 20 Jul 2021 00:16:43 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Tue, 20 Jul 2021 00:16:43 -0500 Received: from [10.24.69.20] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 16K5GeGk048116; Tue, 20 Jul 2021 00:16:41 -0500 Subject: Re: [PATCH 3/4] arm64: dts: ti: k3-am642-sk: Add ecap0 node To: Nishanth Menon CC: , Device Tree Mailing List , Rob Herring , Linux ARM Mailing List , References: <20210719085402.28569-1-lokeshvutla@ti.com> <20210719085402.28569-4-lokeshvutla@ti.com> <20210719152326.op7ii76nvk5sve2a@fringe> From: Lokesh Vutla Message-ID: Date: Tue, 20 Jul 2021 10:46:40 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210719152326.op7ii76nvk5sve2a@fringe> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 19/07/21 8:53 pm, Nishanth Menon wrote: > On 14:24-20210719, Lokesh Vutla wrote: >> ecap0 can be configured to use pad ECAP0_IN_APWM_OUT (D18) which has a >> signal connected to Pin 1 of J3. Add support for adding this pinmux so >> that pwm can be observed on pin 1 of Header J3 >> >> Signed-off-by: Lokesh Vutla >> Signed-off-by: Vignesh Raghavendra >> --- >> arch/arm64/boot/dts/ti/k3-am642-sk.dts | 12 ++++++++++++ >> 1 file changed, 12 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts >> index d3aa2901e6fd..eb0d10e6e787 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts >> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts >> @@ -210,6 +210,12 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ >> AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ >> >; >> }; >> + >> + main_ecap0_pins_default: main-ecap0-pins-default { >> + pinctrl-single,pins = < >> + AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ >> + >; >> + }; >> }; >> >> &mcu_uart0 { >> @@ -453,3 +459,9 @@ &pcie0_rc { >> &pcie0_ep { >> status = "disabled"; >> }; >> + >> +&ecap0 { >> + /* PWM is available on Pin 1 of header J3 */ >> + pinctrl-names = "default"; >> + pinctrl-0 = <&main_ecap0_pins_default>; >> +}; >> -- >> 2.30.0 >> > > > Do the other ecap and pwm nodes need to be disabled since they may not > be pinned out? Sure, Ill mark other ecap and epwm nodes as disabled. After looking at schematics, epwm4 and 5 is pinned out on RPI header. But the header will most likely be used for other use-cases. Shall I mark epwm4 and epwm5 disabled as well with a comment with this information? Thanks and regards, Lokesh >