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[83.9.31.184]) by smtp.gmail.com with ESMTPSA id bd8-20020a05651c168800b0027781448499sm1976368ljb.85.2022.12.28.05.39.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 28 Dec 2022 05:39:08 -0800 (PST) Message-ID: Date: Wed, 28 Dec 2022 14:39:07 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH 10/16] clk: qcom: gcc-sc7180: get rid of test clock Content-Language: en-US To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20221228133243.3052132-1-dmitry.baryshkov@linaro.org> <20221228133243.3052132-11-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20221228133243.3052132-11-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 28.12.2022 14:32, Dmitry Baryshkov wrote: > The test clock apparently it's not used by anyone upstream. Remove it. > > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Konrad Dybcio Konrad > drivers/clk/qcom/gcc-sc7180.c | 16 ---------------- > 1 file changed, 16 deletions(-) > > diff --git a/drivers/clk/qcom/gcc-sc7180.c b/drivers/clk/qcom/gcc-sc7180.c > index 2d3980251e78..105c4762ca84 100644 > --- a/drivers/clk/qcom/gcc-sc7180.c > +++ b/drivers/clk/qcom/gcc-sc7180.c > @@ -23,7 +23,6 @@ > > enum { > P_BI_TCXO, > - P_CORE_BI_PLL_TEST_SE, > P_GPLL0_OUT_EVEN, > P_GPLL0_OUT_MAIN, > P_GPLL1_OUT_MAIN, > @@ -162,21 +161,18 @@ static const struct parent_map gcc_parent_map_0[] = { > { P_BI_TCXO, 0 }, > { P_GPLL0_OUT_MAIN, 1 }, > { P_GPLL0_OUT_EVEN, 6 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_0[] = { > { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, > { .hw = &gpll0.clkr.hw }, > { .hw = &gpll0_out_even.clkr.hw }, > - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, > }; > > static const struct clk_parent_data gcc_parent_data_0_ao[] = { > { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" }, > { .hw = &gpll0.clkr.hw }, > { .hw = &gpll0_out_even.clkr.hw }, > - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, > }; > > static const struct parent_map gcc_parent_map_1[] = { > @@ -184,7 +180,6 @@ static const struct parent_map gcc_parent_map_1[] = { > { P_GPLL0_OUT_MAIN, 1 }, > { P_GPLL6_OUT_MAIN, 2 }, > { P_GPLL0_OUT_EVEN, 6 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_1[] = { > @@ -192,7 +187,6 @@ static const struct clk_parent_data gcc_parent_data_1[] = { > { .hw = &gpll0.clkr.hw }, > { .hw = &gpll6.clkr.hw }, > { .hw = &gpll0_out_even.clkr.hw }, > - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, > }; > > static const struct parent_map gcc_parent_map_2[] = { > @@ -201,7 +195,6 @@ static const struct parent_map gcc_parent_map_2[] = { > { P_GPLL1_OUT_MAIN, 4 }, > { P_GPLL4_OUT_MAIN, 5 }, > { P_GPLL0_OUT_EVEN, 6 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_2[] = { > @@ -210,19 +203,16 @@ static const struct clk_parent_data gcc_parent_data_2[] = { > { .hw = &gpll1.clkr.hw }, > { .hw = &gpll4.clkr.hw }, > { .hw = &gpll0_out_even.clkr.hw }, > - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, > }; > > static const struct parent_map gcc_parent_map_3[] = { > { P_BI_TCXO, 0 }, > { P_GPLL0_OUT_MAIN, 1 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_3[] = { > { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, > { .hw = &gpll0.clkr.hw }, > - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, > }; > > static const struct parent_map gcc_parent_map_4[] = { > @@ -230,7 +220,6 @@ static const struct parent_map gcc_parent_map_4[] = { > { P_GPLL0_OUT_MAIN, 1 }, > { P_SLEEP_CLK, 5 }, > { P_GPLL0_OUT_EVEN, 6 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_4[] = { > @@ -238,7 +227,6 @@ static const struct clk_parent_data gcc_parent_data_4[] = { > { .hw = &gpll0.clkr.hw }, > { .fw_name = "sleep_clk", .name = "sleep_clk" }, > { .hw = &gpll0_out_even.clkr.hw }, > - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, > }; > > static const struct parent_map gcc_parent_map_5[] = { > @@ -246,7 +234,6 @@ static const struct parent_map gcc_parent_map_5[] = { > { P_GPLL0_OUT_MAIN, 1 }, > { P_GPLL7_OUT_MAIN, 3 }, > { P_GPLL0_OUT_EVEN, 6 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_5[] = { > @@ -254,21 +241,18 @@ static const struct clk_parent_data gcc_parent_data_5[] = { > { .hw = &gpll0.clkr.hw }, > { .hw = &gpll7.clkr.hw }, > { .hw = &gpll0_out_even.clkr.hw }, > - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, > }; > > static const struct parent_map gcc_parent_map_6[] = { > { P_BI_TCXO, 0 }, > { P_GPLL0_OUT_MAIN, 1 }, > { P_SLEEP_CLK, 5 }, > - { P_CORE_BI_PLL_TEST_SE, 7 }, > }; > > static const struct clk_parent_data gcc_parent_data_6[] = { > { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, > { .hw = &gpll0.clkr.hw }, > { .fw_name = "sleep_clk", .name = "sleep_clk" }, > - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, > }; > > static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {