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Thu, 13 Mar 2025 11:57:49 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 52DBvmiF028615 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 13 Mar 2025 11:57:48 GMT Received: from [10.217.216.178] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 13 Mar 2025 04:57:44 -0700 Message-ID: Date: Thu, 13 Mar 2025 17:27:40 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc To: Luca Weiss , Dmitry Baryshkov , Vladimir Zapolskiy CC: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Michael Turquette , Stephen Boyd , Conor Dooley , , , References: <20250303225521.1780611-1-vladimir.zapolskiy@linaro.org> <20250303225521.1780611-3-vladimir.zapolskiy@linaro.org> <3210a484-b9c3-4399-bee1-9f5bbc90034c@linaro.org> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KIMEmnqJHATUj4x8LX3ybJ73x5S5LXyH X-Proofpoint-GUID: KIMEmnqJHATUj4x8LX3ybJ73x5S5LXyH X-Authority-Analysis: v=2.4 cv=TIhFS0la c=1 sm=1 tr=0 ts=67d2c83d cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=EzFUx7Xx5Uxcnu-jchQA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-13_05,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 mlxlogscore=595 mlxscore=0 clxscore=1011 bulkscore=0 malwarescore=0 suspectscore=0 spamscore=0 phishscore=0 impostorscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503130094 On 3/13/2025 1:22 PM, Luca Weiss wrote: > Hi Taniya, > > On Thu Mar 13, 2025 at 5:39 AM CET, Taniya Das wrote: >> >> >> On 3/4/2025 2:10 PM, Dmitry Baryshkov wrote: >>> On Tue, 4 Mar 2025 at 09:37, Vladimir Zapolskiy >>> wrote: >>>> >>>> On 3/4/25 01:53, Dmitry Baryshkov wrote: >>>>> On Tue, Mar 04, 2025 at 12:55:21AM +0200, Vladimir Zapolskiy wrote: >>>>>> SM8550 Camera Clock Controller shall enable both MXC and MMCX power >>>>>> domains. >>>>> >>>>> Are those really required to access the registers of the cammcc? Or is >>>>> one of those (MXC?) required to setup PLLs? Also, is this applicable >>>>> only to sm8550 or to other similar clock controllers? >>>> >>>> Due to the described problem I experience a fatal CPU stall on SM8550-QRD, >>>> not on any SM8450 or SM8650 powered board for instance, however it does >>>> not exclude an option that the problem has to be fixed for other clock >>>> controllers, but it's Qualcomm to confirm any other touched platforms, >>> >>> Please work with Taniya to identify used power domains. >>> >> >> CAMCC requires both MMCX and MXC to be functional. > > Could you check whether any clock controllers on SM6350/SM7225 (Bitra) > need multiple power domains, or in general which clock controller uses > which power domain. > > That SoC has camcc, dispcc, gcc, gpucc, npucc and videocc. > > That'd be highly appreciated since I've been hitting weird issues there > that could be explained by some missing power domains. > Hi Luca, The targets you mentioned does not have any have multiple rail dependency, but could you share the weird issues with respect to clock controller I can take a look. > Regards > Luca > >> >>>> for instance x1e80100-camcc has it resolved right at the beginning. >>>> >>>> To my understanding here 'required-opps' shall also be generalized, so >>>> the done copy from x1e80100-camcc was improper, and the latter dt-binding >>>> should be fixed. >>> >>> Yes >>> >> >> required-opps is not mandatory for MXC as we ensure that MxC would never >> hit retention. >> >> https://lore.kernel.org/r/20240625-avoid_mxc_retention-v2-1-af9c2f549a5f@quicinc.com >> >> >>> >>> >